Datasheet AP7315Q (Diodes) - 2
| 制造商 | Diodes |
| 描述 | Automotive Compliant 150MA High Psrr Low Noise Ldo With Enable |
| 页数 / 页 | 12 / 2 — AP7315Q. Pin Descriptions. Pin Number. Pin Name. Function. Functional … |
| 文件格式/大小 | PDF / 543 Kb |
| 文件语言 | 英语 |
AP7315Q. Pin Descriptions. Pin Number. Pin Name. Function. Functional Block Diagram. D E C. ADVAN. AP7315Q (Non Discharge)
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AP7315Q Pin Descriptions Pin Number Pin Name Function
1 VIN Power Input Pin 2 GND Ground Enable Pin
N
3 EN This pin should be driven either high or low and must not be floating.
IO
Driving this pin high enables the regulator, and pulling it low puts the regulator into shutdown mode. 4 NC No Connection
AT
5 VOUT Power Output Pin
RM O F Functional Block Diagram N I D E C
V V V IN OUT VIN OUT - - + +
ADVAN
VREF VREF Current Limit Current Limit EN GND EN GND
AP7315Q (Non Discharge) AP7315DQ (With Discharge) Absolute Maximum Ratings
(Note 5) (@TA = +25°C, unless otherwise specified.)
Symbol Parameter Ratings Unit
ESD HBM Human Body Mode ESD Protection >2 KV ESD CDM Charge Device Model ±500 V VIN Input Voltage 6.0 V VEN Input Voltage EN 6.0 V VOUT Output Voltage -0.3 to VIN +0.3 V IOUT Output Current 300 mA PD Power Dissipation 400 mW TJ Operating Junction Temperature -40 to +150 °C TSTG Storage Temperature -55 to +150 °C Note: 5. a) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability. b). Ratings apply to ambient temperature at +25°C. The JEDEC High-K board design used to derive this data is a 2in. × 2in. multilayer board with 1oz. internal power and ground planes and 2oz. copper traces on the top and bottom of the board. AP7315Q 2 of 12 March 2019 Document number: DS41596 Rev. 1 - 2
www.diodes.com
© Diodes Incorporated Document Outline Pin Assignments Description Applications Features
1 VIN Power Input Pin 2 GND Ground Enable Pin
N
3 EN This pin should be driven either high or low and must not be floating.
IO
Driving this pin high enables the regulator, and pulling it low puts the regulator into shutdown mode. 4 NC No Connection
AT
5 VOUT Power Output Pin
RM O F Functional Block Diagram N I D E C
V V V IN OUT VIN OUT - - + +
ADVAN
VREF VREF Current Limit Current Limit EN GND EN GND
AP7315Q (Non Discharge) AP7315DQ (With Discharge) Absolute Maximum Ratings
(Note 5) (@TA = +25°C, unless otherwise specified.)
Symbol Parameter Ratings Unit
ESD HBM Human Body Mode ESD Protection >2 KV ESD CDM Charge Device Model ±500 V VIN Input Voltage 6.0 V VEN Input Voltage EN 6.0 V VOUT Output Voltage -0.3 to VIN +0.3 V IOUT Output Current 300 mA PD Power Dissipation 400 mW TJ Operating Junction Temperature -40 to +150 °C TSTG Storage Temperature -55 to +150 °C Note: 5. a) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability. b). Ratings apply to ambient temperature at +25°C. The JEDEC High-K board design used to derive this data is a 2in. × 2in. multilayer board with 1oz. internal power and ground planes and 2oz. copper traces on the top and bottom of the board. AP7315Q 2 of 12 March 2019 Document number: DS41596 Rev. 1 - 2
www.diodes.com
© Diodes Incorporated Document Outline Pin Assignments Description Applications Features