Datasheet PIC16F18855, PIC16F18875, PIC16LF18855, PIC16LF18875 (Microchip) - 33

PIC16(L)F18855/75 2.0 ENHANCED MID-RANGE CPU
Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read This family of devices contains an enhanced mid-range program and data memory. 8-bit CPU core. The CPU has 49 instructions. Interrupt • Automatic Interrupt Context Saving capability includes automatic context saving. The hardware stack is 16-levels deep and has Overflow and • 16-level Stack with Overflow and Underflow Underflow Reset capability. Direct, Indirect, and • File Select Registers • Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
15 Configuration 15 Data Dat Bus 8 a Bus a Prog Pro r g am C am o C un o te un r te Nonvolatile MUX Memory 8 Leve 8 Le 16-Le l ve ve St S a t l St c a k c ack RAM (13-b (15-bit) Progr g am a 14 Program Memory RAM Addr Bus 12 Bus Read (PMR) Addr MUX Addr Instruction reg Instruction Reg Indirect Dire Di ct Ad re dr ct Ad 7 Addr 5 12 12 15 FSR reg BSR Reg FS F R re FS SR0 g R re Reg FSR re FSR r g FSR1 Reg 15 STA ST T A US reg US Reg 8 3 MUX Power-up Timer Instru Instr ction Oscillator Decode & Decode and Start-up Timer ALU Control Power-on OSC1/CLKIN Reset 8 Tim Ti ing n Watchdog OSC2/CLKOUT Generatio t n Timer W reg Brown-out Reset Internal Oscillator Block VDD V VSS V  2015-2018 Microchip Technology Inc. DS40001802F-page 33 Document Outline Description PIC16(L)F188XX Family Types Pin Diagrams Pin Allocation Tables Table of Contents 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit naming conventions 1.1.1 Register Names 1.1.2 Bit Names 1.1.2.1 Short Bit Names 1.1.2.2 Long Bit Names 1.1.2.3 Bit Fields 1.1.3 Register and Bit Naming Exceptions 1.1.3.1 Status, Interrupt, and Mirror Bits 1.1.3.2 Legacy Peripherals FIGURE 1-1: PIC16(L)F18855/75 Block Diagram TABLE 1-2: PIC16F18855 Pinout Description TABLE 1-3: PIC16F18875 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F18855/75 3.1.1 Reading Program Memory as Data 3.1.1.1 RETLW Instruction EXAMPLE 3-1: RETLW Instruction 3.1.1.2 Indirect Read with FSR EXAMPLE 3-2: Accessing Program Memory Via FSR 3.2 Data Memory Organization 3.2.1 Core Registers TABLE 3-2: Core Registers 3.2.1.1 STATUS Register Register 3-1: STATUS: STATUS Register 3.2.2 Special Function Register 3.2.3 General Purpose RAM 3.2.3.1 Linear Access to GPR 3.2.4 Common RAM FIGURE 3-2: Banked Memory Partitioning 3.2.5 Device Memory Maps TABLE 3-3: PIC16(L)F18855 Memory Map Bank 0-7 TABLE 3-4: PIC16(L)F18875 Memory Map Bank 0-7 TABLE 3-5: PIC16F18855/75 Memory Map Bank 8-15 TABLE 3-6: PIC16F18855/75 Memory Map Bank 16-23 TABLE 3-7: PIC16(L)F18855/75 Memory Map Bank 24-31 TABLE 3-8: PIC16(L)F18855/75 Memory Map, Bank 28 TABLE 3-9: PIC16(L)F18855/75 Memory Map, Bank 29 TABLE 3-10: PIC16(L)F18855 Memory Map, Bank 30 TABLE 3-11: PIC16(L)F18875 Memory Map, Bank 30 TABLE 3-12: Special Function Register Summary Banks 0-31 (ALL BANKS) TABLE 3-13: Special Function Register Summary Banks 0-31 3.3 PCL and PCLATH FIGURE 3-3: Loading Of PC In Different Situations 3.3.1 Modifying PCL 3.3.2 computed goto 3.3.3 Computed Function Calls 3.3.4 Branching 3.4 Stack 3.4.1 Accessing the Stack FIGURE 3-4: Accessing the Stack Example 1 FIGURE 3-5: Accessing the Stack Example 2 FIGURE 3-6: Accessing the Stack Example 3 FIGURE 3-7: Accessing the Stack Example 4 3.4.2 Overflow/Underflow Reset 3.5 Indirect Addressing FIGURE 3-8: Indirect Addressing 3.5.1 Traditional Data Memory FIGURE 3-9: Traditional Data Memory Map 3.5.2 Linear Data Memory FIGURE 3-10: Traditional Data Memory Map 3.5.3 Data EEPROM Memory 3.5.4 Program Flash Memory FIGURE 3-11: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words TABLE 4-1: Configuration Word Locations 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1: Oscillators Register 4-2: CONFIG2: Configuration Word 2: Supervisors Register 4-3: CONFIG3: Configuration Word 3: Windowed Watchdog Register 4-4: CONFIG4: Configuration Word 4: Memory Register 4-5: CONFIG5: Configuration Word 5: Code Protection 4.3 Code Protection 4.3.1 Program Memory Protection 4.3.2 Data memory protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-6: DevID: Device ID Register Register 4-7: RevisionID: Revision ID Register 5.0 Resets FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) TABLE 5-1: BOR Operating Modes 5.2.1 BOR is Always On 5.2.2 BOR is Off in Sleep 5.2.3 BOR Controlled by Software 5.2.4 BOR is always OFF FIGURE 5-2: Brown-Out Situations 5.3 Register Definitions: Brown-out Reset Control Register 5-1: BORCON: Brown-out Reset Control Register 5.4 MCLR TABLE 5-2: MCLR Configuration 5.4.1 MCLR Enabled 5.4.2 MCLR Disabled 5.5 Windowed Watchdog Timer (WWDT) Reset 5.6 RESET Instruction 5.7 Stack Overflow/Underflow Reset 5.8 Programming Mode Exit 5.9 Power-Up Timer 5.10 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.11 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.12 Power Control (PCON) Register 5.13 Register Definitions: Power Control Register 5-2: PCON0: Power Control Register 0 TABLE 5-5: Summary of Registers Associated with Resets 6.0 Oscillator Module (with Fail-Safe Clock Monitor) 6.1 Overview FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram 6.2 Clock Source Types 6.2.1 External Clock Sources 6.2.1.1 EC Mode FIGURE 6-2: External Clock (EC) Mode Operation 6.2.1.2 LP, XT, HS Modes FIGURE 6-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 6-4: Ceramic Resonator Operation (XT or HS Mode) 6.2.1.3 Oscillator Start-up Timer (OST) 6.2.1.4 4x PLL 6.2.1.5 Secondary Oscillator FIGURE 6-5: Quartz Crystal Operation (Secondary Oscillator) 6.2.2 Internal Clock Sources 6.2.2.1 HFINTOSC 6.2.2.2 Internal Oscillator Frequency Adjustment 6.2.2.3 LFINTOSC 6.2.2.4 MFINTOSC 6.2.2.5 Oscillator Status and Manual Enable 6.3 Clock Switching 6.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) BITS 6.3.2 PLL Input Switch 6.3.3 Clock Switch and Sleep FIGURE 6-6: Clock Switch (CSWHOLD = 0) FIGURE 6-7: Clock Switch (CSWHOLD = 1) FIGURE 6-8: Clock Switch Abandoned 6.4 Fail-Safe Clock Monitor FIGURE 6-9: FSCM Block Diagram 6.4.1 Fail-Safe Detection 6.4.2 Fail-Safe Operation 6.4.3 Fail-Safe Condition Clearing 6.4.4 Reset or Wake-up from Sleep FIGURE 6-10: FSCM Timing Diagram 6.5 Register Definitions: Oscillator Control Register 6-1: OSCCON1: Oscillator Control Register1 Register 6-2: OSCCON2: Oscillator Control Register 2 TABLE 6-1: NOSC/COSC Bit Settings TABLE 6-2: NDIV/CDIV Bit Settings Register 6-3: OSCCON3: Oscillator Control Register 3 Register 6-4: OSCSTAT: Oscillator STATUS Register 1 Register 6-5: OSCEN: Oscillator Manual Enable Register Register 6-6: OSCFRQ: HFINTOSC Frequency Selection Register Register 6-7: OSCTUNE: HFINTOSC Tuning Register TABLE 6-3: Summary of Registers Associated with Clock Sources TABLE 6-4: Summary OF Configuration Word WITH Clock Sources 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE0: Peripheral Interrupt Enable Register 0 Register 7-3: PIE1: Peripheral Interrupt Enable Register 1 Register 7-4: PIE2: Peripheral Interrupt Enable Register 2 Register 7-5: PIE3: Peripheral Interrupt Enable Register 3 Register 7-6: PIE4: Peripheral Interrupt Enable Register 4 Register 7-7: PIE5: Peripheral Interrupt Enable Register 5 Register 7-8: PIE6: Peripheral Interrupt Enable Register 6 Register 7-9: PIE7: Peripheral Interrupt Enable Register 7 Register 7-10: PIE8: Peripheral Interrupt Enable Register 8 Register 7-11: PIR0: Peripheral Interrupt Status Register 0 Register 7-12: PIR1: Peripheral Interrupt Request Register 1 Register 7-13: PIR2: Peripheral Interrupt Request Register 2 Register 7-14: PIR3: Peripheral Interrupt Request Register 3 Register 7-15: PIR4: Peripheral Interrupt Request Register 4 Register 7-16: PIR5: Peripheral Interrupt Request Register 5 Register 7-17: PIR6: Peripheral Interrupt Request Register 6 Register 7-18: PIR6: Peripheral Interrupt Request Register 6 Register 7-19: PIR7: Peripheral Interrupt Request Register 7 Register 7-20: PIR8: Peripheral Interrupt Request Register 8 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Saving Operation Modes 8.1 DOZE Mode FIGURE 8-1: DOZE Mode Operation Example 8.1.1 Doze Operation 8.1.2 Interrupts During Doze 8.2 Sleep Mode 8.2.1 Wake-up from Sleep 8.2.2 Wake-up Using Interrupts FIGURE 8-2: Wake-Up From Sleep Through Interrupt 8.2.3 Low-Power Sleep Mode 8.2.3.1 Sleep Current vs. Wake-up Time 8.2.3.2 Peripheral Usage in Sleep 8.2.4 IDLE Mode 8.2.4.1 Idle and Interrupts 8.2.4.2 Idle and WDT 8.3 Register Definitions: Voltage Regulator and DOZE Control Register 8-1: VREGCON: Voltage Regulator Control Register (1) Register 8-2: CPUDOZE: Doze and Idle Register TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Windowed Watchdog Timer (WWDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes 9.2.1 WDT Is Always On 9.2.2 WDT Is Off In Sleep 9.2.3 WDT Controlled by Software TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Watchdog Window 9.5 Clearing the WDT 9.5.1 CLRWDT Considerations (Windowed Mode) 9.6 Operation During Sleep TABLE 9-2: WDT Clearing Conditions FIGURE 9-2: Window Period and Delay 9.7 Register Definitions: Windowed Watchdog Timer Control Register 9-1: WDTCON0: Watchdog Timer Control Register 0 Register 9-2: WDTCON1: Watchdog Timer Control Register 1 Register 9-3: WDTPSL: WDT Prescale Select Low Byte Register (Read-Only) Register 9-4: WDTPSH: WDT Prescale Select High Byte Register (Read-Only) Register 9-5: WDTTMR: WDT Timer Register (Read-Only) TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary OF Configuration Word WITH Watchdog Timer 10.0 Nonvolatile Memory (NVM) Control 10.1 Program Flash Memory (PFM) TABLE 10-1: Flash Memory Organization by Device 10.1.1 Program Memory Voltages 10.1.1.1 Programming Externally 10.1.1.2 Self-programming 10.2 Data EEPROM Memory 10.3 FSR and INDF Access 10.3.1 FSR Read 10.3.2 FSR Write 10.4 NVMREG Access 10.4.1 NVMREG Read Operation FIGURE 10-1: Flash Program Memory Read Flowchart EXAMPLE 10-1: PFM Program Memory Read 10.4.2 NVM Unlock Sequence FIGURE 10-2: NVM Unlock Sequence Flowchart EXAMPLE 10-2: NVM Unlock Sequence 10.4.3 NVMREG Write to EEPROM 10.4.4 NVMREG Erase of PFM FIGURE 10-3: NVM Erase Flowchart EXAMPLE 10-3: Erasing One Row of Program Flash Memory (PFM) TABLE 10-2: NVM Organization and Access Information 10.4.5 NVMREG Write to PFM FIGURE 10-4: Block Writes to Program Flash Memory (PFM) With 32 write latches FIGURE 10-5: Program Flash Memory (PFM) Write Flowchart EXAMPLE 10-4: Writing to Program Flash Memory (PFM) 10.4.6 Modifying Flash Program Memory FIGURE 10-6: Flash Program Memory Modify Flowchart 10.4.7 NVMREG Data EEPROM Memory, User ID, Device ID and Configuration Word Access FIGURE 10-7: Flash Program Memory Modify Flowchart TABLE 10-3: EEPROM, User ID, Dev/REV ID and Configuration Word Access (NVMREGS = 1) EXAMPLE 10-5: Device ID Access 10.4.8 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.4.9 WRERR Bit TABLE 10-4: Actions for PFM When WR = 1 10.5 Register Definitions: Flash Program Memory Control Register 10-1: NVMDATL: Nonvolatile Memory Data Low Byte Register Register 10-2: NVMDATH: Nonvolatile Memory Data High Byte Register Register 10-3: NVMADRL: Nonvolatile Memory Address Low Byte Register Register 10-4: NVMADRH: Nonvolatile Memory Address High Byte Register Register 10-5: NVMCON1: Nonvolatile Memory Control 1 Register Register 10-6: NVMCON2: NONVOLATILE Memory Control 2 Register TABLE 10-5: Summary of Registers Associated with Nonvolatile Memory (NVM) 11.0 Cyclic Redundancy Check (CRC) Module 11.1 CRC Module Overview 11.2 CRC Functional Overview EXAMPLE 11-1: Basic CRC Operation Example 11.3 CRC Polynomial Implementation FIGURE 11-1: CRC LFSR Example 11.4 CRC Data Sources 11.4.1 CRC from User Data 11.4.2 CRC from Flash 11.5 CRC Check Value 11.6 CRC Interrupt 11.7 Configuring the CRC 11.8 Program Memory Scan Configuration 11.9 Scanner Interrupt 11.10 Scanning Modes 11.10.1 Burst Mode 11.10.2 Concurrent Mode 11.10.3 Triggered mode 11.10.4 Peek Mode TABLE 11-1: Summary of Scanner Modes 11.10.5 Interrupt Interaction TABLE 11-2: Scan Interrupt Modes 11.10.6 WDT interaction 11.10.7 In-Circuit Debug (ICD) INTERACTION TABLE 11-3: ICD and Scanner Interactions 11.11 Register Definitions: CRC and Scanner Control Register 11-1: CRCCON0: CRC Control Register 0 Register 11-2: CRCCON1: CRC Control Register 1 Register 11-3: CRCDATH: CRC Data High Byte Register Register 11-4: CRCDATL: CRC Data Low Byte Register Register 11-5: CRCACCH: CRC Accumulator High Byte Register Register 11-6: CRCACCL: CRC Accumulator Low Byte Register Register 11-7: CRCSHIFTH: CRC Shift High Byte Register Register 11-8: CRCSHIFTL: CRC Shift Low Byte Register Register 11-9: CRCXORH: CRC XOR High Byte Register Register 11-10: CRCXORL: CRC XOR Low Byte Register Register 11-11: SCANCON0: Scanner Access Control Register 0 Register 11-12: SCANLADRH: SCAN Low Address High Byte Register Register 11-13: SCANLADRL: SCAN Low Address Low Byte Register Register 11-14: SCANHADRH: SCAN High Address High Byte Register Register 11-15: SCANHADRL: SCAN High Address Low Byte Register Register 11-16: SCANTRIG: SCAN Trigger Selection Register TABLE 11-4: Summary of Registers Associated with CRC 12.0 I/O Ports TABLE 12-1: Port Availability Per Device FIGURE 12-1: Generic I/O Port Operation 12.1 I/O Priorities 12.2 PORTA Registers 12.2.1 Data Register EXAMPLE 12-1: Initializing PORTA 12.2.2 Direction Control 12.2.3 Open-Drain Control 12.2.4 Slew Rate Control 12.2.5 Input Threshold Control 12.2.6 Analog Control 12.2.7 Weak Pull-up Control 12.2.8 PORTA Functions and Output Priorities 12.3 Register Definitions: PORTA Register 12-1: PORTA: PORTA Register Register 12-2: TRISA: PORTA Tri-State Register Register 12-3: LATA: PORTA Data Latch Register Register 12-4: ANSELA: PORTA Analog Select Register Register 12-5: WPUA: Weak Pull-Up PORTA Register Register 12-6: ODCONA: PORTA Open-Drain Control Register Register 12-7: SLRCONA: PORTA Slew Rate Control Register Register 12-8: INLVLA: PORTA Input Level Control Register TABLE 12-2: Summary of Registers Associated with PORTA 12.4 PORTB Registers 12.4.1 Data Register EXAMPLE 12-2: Initializing PORTA 12.4.2 Direction Control 12.4.3 Open-Drain Control 12.4.4 Slew Rate Control 12.4.5 Input Threshold Control 12.4.6 Analog Control 12.4.7 Weak Pull-up Control 12.4.8 PORTA Functions and Output Priorities 12.5 Register Definitions: PORTB Register 12-9: PORTB: PORTB Register Register 12-10: TRISB: PORTB Tri-State Register Register 12-11: LATB: PORTB Data Latch Register Register 12-12: ANSELB: PORTB Analog Select Register Register 12-13: WPUB: Weak Pull-Up PORTB Register Register 12-14: ODCONB: PORTB Open-Drain Control Register Register 12-15: SLRCONB: PORTB Slew Rate Control Register Register 12-16: INLVLB: PORTB Input Level Control Register TABLE 12-3: Summary of Registers Associated with PORTB 12.6 PORTC Registers 12.6.1 Data Register 12.6.2 Direction Control 12.6.3 Input Threshold Control 12.6.4 Open-Drain Control 12.6.5 Slew Rate Control 12.6.6 Analog Control 12.6.7 Weak Pull-up Control 12.6.8 PORTC Functions and Output Priorities 12.7 Register Definitions: PORTC Register 12-17: PORTC: PORTC Register Register 12-18: TRISC: PORTC Tri-State Register Register 12-19: LATC: PORTC Data Latch Register Register 12-20: ANSELC: PORTC Analog Select Register Register 12-21: WPUC: Weak Pull-Up PORTC Register Register 12-22: ODCONC: PORTC Open-Drain Control Register Register 12-23: SLRCONC: PORTC Slew Rate Control Register Register 12-24: INLVLC: PORTC Input Level Control Register TABLE 12-4: Summary of Registers Associated with PORTC 12.8 PORTD Registers (PIC16(L)F18875 only) 12.8.1 Data Register Control 12.8.2 Direction Control 12.8.3 Input Threshold Control 12.8.4 Open-Drain Control 12.8.5 Slew Rate Control 12.8.6 Analog Control 12.8.7 Weak Pull-up Control 12.8.8 PORTD Functions and Output Priorities 12.9 Register Definitions: PORTD Register 12-25: PORTD: PORTD Register Register 12-26: TRISD: PORTD Tri-State Register Register 12-27: LATD: PORTD Tri-State Register Register 12-28: ANSELD: PORTD Tri-State Register Register 12-29: WPUD: Weak Pull-up PORTD Register Register 12-30: ODCOND: PORTD Open-Drain Control Register Register 12-31: SLRCOND: PORTD Slew Rate Control Register Register 12-32: INLVLD: PORTD Input Level Control Register TABLE 12-5: Summary of Registers Associated with PORTD(1) 12.10 PORTE Registers (PIC16(L)F18855) 12.10.1 Data Register 12.10.2 Input Threshold Control 12.10.3 Weak Pull-up Control 12.10.4 PORTE Functions and Output Priorities 12.11 Register Definitions: PORTE (PIC16(L)F18855) Register 12-33: PORTE: PORTE Register Register 12-34: WPUE: WEAK PULL-uP PORTe REGISTER Register 12-35: INLVLE: PORTE Input Level Control Register TABLE 12-6: Summary of Registers Associated with PORTE TABLE 12-7: Summary of Configuration Word with PORTE 12.12 PORTE Registers (PIC16(L)F18875) 12.12.1 Data Register 12.12.2 Direction Control 12.12.3 Input Threshold Control 12.12.4 Open-Drain Control 12.12.5 Slew Rate Control 12.12.6 Analog Control 12.12.7 Weak Pull-up Control 12.12.8 PORTE Functions and Output Priorities 12.12.9 PORTE Functions and Output Priorities 12.13 Register Definitions: PORTE (PIC16(L)F18875) Register 12-36: PORTE: PORTE Register Register 12-37: TRISE: PORTE Tri-State Register Register 12-38: LATE: PORTE Data Latch Register Register 12-39: ANSELE: PORTE Analog Select Register Register 12-40: WPUE: WEAK PULL-uP PORTe REGISTER Register 12-41: ODCONE: PORTE Open-Drain Control Register Register 12-42: SLRCONE: PORTE Slew Rate Control Register Register 12-43: INLVLE: PORTE Input Level Control Register TABLE 12-8: Summary of Registers Associated with PORTE(1) TABLE 12-9: Summary of Configuration Word with PORTE 13.0 Peripheral Pin Select (PPS) Module TABLE 13-1: PPS Input Signal Routing Options TABLE 13-2: PPS Input Register Values 13.1 PPS Inputs 13.2 PPS Outputs FIGURE 13-1: Simplified PPS Block Diagram 13.3 Bidirectional Pins 13.4 PPS Lock EXAMPLE 13-1: PPS Lock/Unlock sequence 13.5 PPS Permanent Lock 13.6 Operation During Sleep 13.7 Effects of a Reset TABLE 13-3: PPS Output Signal Routing Options 13.8 Register Definitions: PPS Input Selection Register 13-1: xxxPPS: Peripheral xxx input Selection(1) Register 13-2: RxyPPS: Pin Rxy Output Source Selection Register Register 13-3: PPSLOCK: PPS Lock Register TABLE 13-4: Summary of Registers Associated with the PPS Module 14.0 Peripheral Module Disable 14.1 Disabling a Module 14.2 Enabling a module 14.3 Disabling a Module 14.4 System Clock Disable Register 14-1: PMD0: PMD Control Register 0 Register 14-2: PMD1: PMD Control Register 1 Register 14-3: PMD2: PMD Control Register 2 Register 14-4: PMD3: PMD Control Register 3 Register 14-5: PMD4: PMD Control Register 4 Register 14-6: PMD5 – PMD Control Register 5 15.0 Interrupt-On-Change 15.1 Enabling the Module 15.2 Individual Pin Configuration 15.3 Interrupt Flags 15.4 Clearing Interrupt Flags EXAMPLE 15-1: Clearing Interrupt Flags (PORTA Example) 15.5 Operation in Sleep FIGURE 15-1: Interrupt-On-Change Block Diagram (PORTA Example) 15.6 Register Definitions: Interrupt-on-Change Control Register 15-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 15-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 15-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 15-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register Register 15-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register Register 15-6: IOCBF: Interrupt-on-Change PORTB Flag Register Register 15-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 15-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 15-9: IOCCF: Interrupt-on-Change PORTC Flag Register Register 15-10: IOCEP: Interrupt-on-Change PORTE Positive Edge Register Register 15-11: IOCEN: Interrupt-on-Change PORTE Negative Edge Register Register 15-12: IOCEF: Interrupt-on-Change PORTE Flag Register TABLE 15-1: Summary of Registers Associated with Interrupt-On-Change 16.0 Fixed Voltage Reference (FVR) 16.1 Independent Gain Amplifiers 16.2 FVR Stabilization Period FIGURE 16-1: Voltage Reference Block Diagram 16.3 Register Definitions: FVR Control Register 16-1: FVRCON: Fixed Voltage Reference Control Register TABLE 16-1: Summary of Registers Associated with Fixed Voltage Reference 17.0 Temperature Indicator Module 17.1 Circuit Operation EQUATION 17-1: Vout Ranges FIGURE 17-1: Temperature Circuit Diagram 17.2 Minimum Operating Vdd TABLE 17-1: Recommended Vdd vs. Range 17.3 Temperature Output 17.4 ADC Acquisition Time TABLE 17-2: Summary of Registers Associated with the Temperature Indicator 18.0 Comparator Module 18.1 Comparator Overview TABLE 18-1: Available Comparators FIGURE 18-1: Single Comparator FIGURE 18-2: Comparator Module Simplified Block Diagram 18.2 Comparator Control 18.2.1 Comparator Enable 18.2.2 Comparator Output 18.2.3 Comparator Output Polarity TABLE 18-2: Comparator Output State vs. Input Conditions 18.3 Comparator Hysteresis 18.4 Timer1 Gate Operation 18.4.1 Comparator Output Synchronization 18.5 Comparator Interrupt 18.6 Comparator Positive Input Selection 18.7 Comparator Negative Input Selection 18.8 Comparator Response Time 18.9 Analog Input Connection Considerations FIGURE 18-3: Analog Input Model 18.10 CWG1 Auto-shutdown Source 18.11 Operation in Sleep Mode 18.12 Register Definitions: Comparator Control Register 18-1: CMxCON0: Comparator Cx Control Register 0 Register 18-2: CMxCON1: Comparator Cx Control Register 1 Register 18-3: CMxNSEL: Comparator Cx Negative Input Select Register Register 18-4: CMxPSEL: Comparator Cx Positive Input Select Register Register 18-5: CMOUT: Comparator Output Register TABLE 18-3: Summary of Registers Associated with Comparator Module 19.0 Pulse-Width Modulation (PWM) FIGURE 19-1: PWM Output 19.1 Standard PWM Mode FIGURE 19-2: Simplified PWM Block Diagram 19.1.1 PWM Clock Selection 19.1.2 Using tHE tmr2/4/6 WITH THE pwm mODULE 19.1.3 PWM PERIOD EQUATION 19-1: PWM Period 19.1.4 PWM DUTY CYCLE EQUATION 19-2: Pulse Width EQUATION 19-3: Duty Cycle Ratio 19.1.5 PWM RESOLUTION EQUATION 19-4: PWM Resolution 19.1.6 OPERATION IN SLEEP MODE 19.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY 19.1.8 EFFECTS OF RESET TABLE 19-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 19-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 19.1.9 Setup for PWM Operation 19.2 Register Definitions: PWM Control Register 19-1: PWMxCON: PWM Control Register Register 19-2: PWMXDCH: PWM Duty Cycle High Bits Register 19-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 19-3: Summary of Registers Associated with PWMx 20.0 Complementary Waveform Generator (CWG) Module TABLE 20-1: Available CWG Modules 20.1 Fundamental Operation 20.1.1 HALF-BRIDGE MODE FIGURE 20-1: Simplified CWG Block Diagram (Half-Bridge Mode) 20.1.2 PUSH-PULL MODE 20.1.3 FULL-BRIDGE MODES FIGURE 20-2: Simplified CWG Block Diagram (Push-Pull Mode) FIGURE 20-3: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) 20.1.4 STEERING MODES FIGURE 20-4: Simplified CWG Block Diagram (Output Steering Modes) 20.2 Clock Source 20.3 Selectable Input Sources TABLE 20-2: Selectable Input Sources 20.4 Output Control 20.4.1 Output Enables 20.4.2 Polarity Control FIGURE 20-5: CWG Output Block Diagram 20.5 Dead-Band Control 20.5.1 Dead-Band functionality in Half-Bridge mode 20.5.2 Dead-Band functionality in Full-Bridge mode 20.6 Rising Edge and Reverse Dead Band 20.7 Falling Edge and Forward Dead Band FIGURE 20-6: Dead-Band Operation CWGxDBR = 0x01, CWGxDBF = 0x02 FIGURE 20-7: Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x04, Source Shorter Than Dead Band 20.8 Dead-Band Uncertainty EQUATION 20-1: Dead-Band Uncertainty FIGURE 20-8: Example of PWM Direction Change FIGURE 20-9: CWG Half-Bridge Mode Operation 20.9 CWG Steering Mode 20.9.1 Steering Synchronization FIGURE 20-10: Example of Steering Event at End of Instruction (MODE<2:0> = 000) FIGURE 20-11: Example of Steering Event at Beginning of Instruction (MODE<2:0> = 001) 20.10 Auto-Shutdown 20.10.1 SHUTDOWN 20.10.1.1 Software Generated Shutdown 20.10.2 External Input Source 20.11 Operation During Sleep FIGURE 20-12: CWG Shutdown Block Diagram 20.12 Configuring the CWG 20.12.1 Pin Override Levels 20.12.2 Auto-Shutdown Restart 20.12.2.1 Software Controlled Restart 20.12.2.2 Auto-Restart FIGURE 20-13: Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = 01, LSBD = 01) FIGURE 20-14: Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = 01, LSBD = 01) 20.13 Register Definitions: CWG Control TABLE 20-3: Long Bit Names Prefixes for CWG Peripherals Register 20-1: CWGxCON0: CWGX Control Register 0 Register 20-2: CWGxCON1: CWGX Control Register 1 Register 20-3: CWGxDBR: CWGX Rising Dead-Band Counter Register Register 20-4: CWGxDBF: CWGX Falling Dead-Band Counter Register Register 20-5: CWGxAS0: CWGX Auto-Shutdown Control Register 0 Register 20-6: CWGxAS1: CWGX Auto-Shutdown Control Register 1 Register 20-7: CWGxSTR: CWGX Steering Control Register(1) Register 20-8: CWGxCLK: CWGX Clock Selection Register Register 20-9: CWGxISM: CWGX Input Selection Register TABLE 20-4: Summary of Registers Associated with CWG 21.0 Zero-Cross Detection (ZCD) Module 21.1 External Resistor Selection EQUATION 21-1: External Resistor FIGURE 21-1: External Voltage FIGURE 21-2: Simplified ZCD Block Diagram 21.2 ZCD Logic Output 21.3 ZCD Logic Polarity 21.4 ZCD Interrupts 21.5 Correcting for Vcpinv offset 21.5.1 Correction by AC Coupling EQUATION 21-2: R-C Calculations EXAMPLE 21-1: R-C Calculations 21.5.2 Correction By Offset Current EQUATION 21-3: ZCD Event Offset EQUATION 21-4: ZCD Pull-up/down 21.6 Handling Vpeak variations EQUATION 21-5: Series R for V range 21.7 Operation During Sleep 21.8 Effects of a Reset 21.9 Disabling the ZCD Module 21.10 Register Definitions: ZCD Control Register 21-1: ZCDCON: Zero-Cross Detection Control Register TABLE 21-1: Summary of Registers Associated with the ZCD Module TABLE 21-2: Summary of Configuration Word with the ZCD Module 22.0 Configurable Logic Cell (CLC) TABLE 22-1: Available CLC Modules FIGURE 22-1: CLCx Simplified Block Diagram 22.1 CLCx Setup 22.1.1 Data Selection TABLE 22-2: CLCx Data Input Selection 22.1.2 Data Gating TABLE 22-3: Data Gating Logic 22.1.3 Logic Function 22.1.4 Output Polarity 22.2 CLCx Interrupts 22.3 Output Mirror Copies 22.4 Effects of a Reset 22.5 Operation During Sleep 22.6 CLCx Setup Steps FIGURE 22-2: Input Data Selection and Gating FIGURE 22-3: Programmable Logic Functions 22.7 Register Definitions: CLC Control Register 22-1: CLCxCON: Configurable Logic Cell Control Register Register 22-2: CLCxPOL: Signal Polarity Control Register Register 22-3: CLCxSEL0: Generic CLCx Data 0 Select Register Register 22-4: CLCxSEL1: Generic CLCx Data 1 Select Register Register 22-5: CLCxSEL2: Generic CLCx Data 2 Select Register Register 22-6: CLCxSEL3: Generic CLCx Data 3 Select Register Register 22-7: CLCxGLS0: Gate 0 Logic Select Register Register 22-8: CLCxGLS1: Gate 1 Logic Select Register Register 22-9: CLCxGLS2: Gate 2 Logic Select Register Register 22-10: CLCxGLS3: Gate 3 Logic Select Register Register 22-11: CLCDATA: CLC Data Output TABLE 22-4: Summary of Registers Associated with CLCx 23.0 Analog-to-Digital Converter With Computation (ADC2) Module FIGURE 23-1: ADC2 Block Diagram 23.1 ADC Configuration 23.1.1 Port Configuration 23.1.2 Channel Selection 23.1.3 ADC Voltage Reference 23.1.4 Conversion Clock TABLE 23-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 23-2: Analog-to-Digital Conversion Tad Cycles (ADSC = 0) 23.1.5 Interrupts 23.1.6 Result Formatting FIGURE 23-3: 10-Bit ADC Conversion Result Format 23.2 ADC Operation 23.2.1 Starting a Conversion 23.2.2 Completion of a Conversion 23.2.3 Terminating a Conversion 23.2.4 ADC Operation During Sleep 23.2.5 External Trigger During Sleep 23.2.6 Auto-Conversion Trigger TABLE 23-2: ADC Auto-Conversion Table 23.2.7 ADC Conversion Procedure (Basic Mode) EXAMPLE 23-1: ADC Conversion 23.3 ADC Acquisition Requirements EQUATION 23-1: Acquisition Time Example FIGURE 23-4: Analog Input Model FIGURE 23-5: ADC Transfer Function 23.4 Capacitive Voltage Divider (CVD) Features FIGURE 23-6: Hardware Capacitive Voltage Divider Block Diagram 23.4.1 CVD Operation FIGURE 23-7: Differential CVD Measurement Waveform 23.4.2 Precharge Control 23.4.3 Acquisition Control 23.4.4 Guard Ring Outputs FIGURE 23-8: Guard Ring Circuit FIGURE 23-9: Differential CVD WITH Guard Ring Output Waveform 23.4.5 Additional Sample and Hold Capacitance 23.5 Computation Operation FIGURE 23-10: Computational Features Simplified Block Diagram TABLE 23-3: Computation Modes 23.5.1 Digital Filter/Average TABLE 23-4: Lowpass Filter -3 dB Cut-Off Frequency 23.5.2 Basic Mode 23.5.3 Accumulate Mode: 23.5.4 Average Mode 23.5.5 Burst Average Mode 23.5.6 Lowpass Filter Mode 23.5.7 Threshold Comparison 23.5.8 Continuous Sampling Mode 23.5.9 Double Sample Conversion 23.6 Register Definitions: ADC Control Register 23-1: ADCON0: ADC Control Register 0 Register 23-2: ADCON1: ADC Control Register 1 TABLE 23-5: Example of Register Values for Accumulate and Average Modes Register 23-3: ADCON2: ADC Control Register 2 Register 23-4: ADCON3: ADC Threshold Register Register 23-5: ADSTAT: ADC Threshold Register Register 23-6: ADCLK: ADC Clock Selection Register Register 23-7: ADREF: ADC Reference Selection Register Register 23-8: ADPCH: ADC Positive Channel Selection Register Register 23-9: ADPRE: ADC Precharge Time Control Register Register 23-10: ADACQ: ADC Acquisition Time Control Register Register 23-11: ADCAP: ADC Additional Sample Capacitor Selection Register Register 23-12: ADRPT: ADC Repeat Setting Register Register 23-13: ADCNT: ADC Conversion Counter Register Register 23-14: ADFLTRH: ADC Filter High Byte Register Register 23-15: ADFLTRL: ADC Filter Low Byte Register Register 23-16: ADRESH: ADC Result Register High, ADFRM=0 Register 23-17: ADRESL: ADC Result Register Low, ADFRM=0 Register 23-18: ADRESH: ADC Result Register High, ADFRM=1 Register 23-19: ADRESL: ADC Result Register Low, ADFRM=1 Register 23-20: ADPREVH: ADC Previous Result Register Register 23-21: ADPREVL: ADC Previous Result Register Register 23-22: ADACCH: ADC Accumulator Register High Register 23-23: ADACCL: ADC Accumulator Register Low Register 23-24: ADSTPTH: ADC Threshold Setpoint Register High Register 23-25: ADSTPTL: ADC Threshold Setpoint Register Low Register 23-26: ADERRH: ADC Calculation Error Register High Register 23-27: ADERRL: ADC Calculation Error Low Byte Register Register 23-28: ADLTHH: ADC Lower Threshold High Byte Register Register 23-29: ADLTHL: ADC Lower Threshold Low Byte Register Register 23-30: ADUTHH: ADC Upper Threshold High Byte Register Register 23-31: ADUTHL: ADC Upper Threshold Low Byte Register Register 23-32: ADACT: ADC AUTO Conversion Trigger Control Register TABLE 23-6: Summary of Registers Associated with ADC 24.0 Numerically Controlled Oscillator (NCO) Module FIGURE 24-1: Direct Digital Synthesis Module Simplified Block Diagram 24.1 NCO OPERATION EQUATION 24-1: NCO Overflow Frequency 24.1.1 NCO CLOCK SOURCES 24.1.2 ACCUMULATOR 24.1.3 ADDER 24.1.4 INCREMENT REGISTERS 24.2 FIXED DUTY CYCLE MODE 24.3 PULSE FREQUENCY MODE 24.3.1 OUTPUT PULSE WIDTH CONTROL 24.4 OUTPUT POLARITY CONTROL 24.5 Interrupts 24.6 Effects of a Reset 24.7 Operation in Sleep FIGURE 24-2: FDC Output Mode Operation Diagram 24.8 NCO Control Registers Register 24-1: NCO1CON: NCO Control Register Register 24-2: NCO1CLK: NCO1 Input Clock Control Register Register 24-3: NCO1ACCL: NCO1 Accumulator Register – Low Byte Register 24-4: NCO1ACCH: NCO1 Accumulator Register – High Byte Register 24-5: NCO1ACCU: NCO1 Accumulator Register – Upper Byte(1) Register 24-6: NCO1INCL: NCO1 Increment Register – Low Byte(1,2) Register 24-7: NCO1INCH: NCO1 Increment Register – High Byte(1) Register 24-8: NCO1INCU: NCO1 Increment Register – Upper Byte(1) TABLE 24-1: Summary of Registers Associated with NCO 25.0 5-Bit Digital-to-Analog Converter (DAC1) Module 25.1 Output Voltage Selection EQUATION 25-1: DAC Output Voltage 25.2 Ratiometric Output Level 25.3 DAC Voltage Reference Output FIGURE 25-1: Digital-to-Analog Converter Block Diagram FIGURE 25-2: Voltage Reference Output Buffer Example 25.4 Operation During Sleep 25.5 Effects of a Reset 25.6 Register Definitions: DAC Control Register 25-1: DAC1CON0: Voltage Reference Control Register 0 Register 25-2: DAC1CON1: Voltage Reference Control Register 1 TABLE 25-1: Summary of Registers Associated with the DAC1 Module 26.0 Data Signal Modulator (DSM) Module FIGURE 26-1: Simplified Block Diagram of the Data SIgnal Modulator 26.1 DSM Operation 26.2 Modulator Signal Sources 26.3 Carrier Signal Sources 26.4 Carrier Synchronization FIGURE 26-2: On OFF Keying (OOK) Synchronization FIGURE 26-3: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0) FIGURE 26-4: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0) FIGURE 26-5: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1) FIGURE 26-6: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1) 26.5 Carrier Source Polarity Select 26.6 Programmable Modulator Data 26.7 Modulated Output Polarity 26.8 Slew Rate Control 26.9 Operation in Sleep Mode 26.10 Effects of a Reset 26.11 Register Definitions: Modulation Control Register 26-1: MDCON0: Modulation Control Register Register 26-2: MDCON1: Modulation Control Register 1 Register 26-3: MDSRC: Modulation Source Control Register Register 26-4: MDCARH: Modulation High Carrier Control Register Register 26-5: MDCARL: Modulation Low Carrier Control Register Register 26-6: MDSRC: Modulator Source Register TABLE 26-1: Summary of Registers Associated with Data Signal Modulator Mode 27.0 Timer0 Module 27.1 Timer0 Operation 27.1.1 16-Bit Mode 27.1.1.1 Timer0 Reads and Writes in 16-Bit Mode 27.1.2 8-BIT Mode 27.1.3 Counter Mode 27.1.4 Timer Mode 27.1.5 Asynchronous Mode 27.1.6 Synchronous Mode 27.2 Clock Source Selection 27.2.1 Internal Clock Source 27.2.2 External Clock Source 27.3 Programmable Prescaler 27.4 Programmable Postscaler 27.5 Operation during Sleep 27.6 Timer0 Interrupts 27.7 Timer0 Output FIGURE 27-1: Block Diagram of Timer0 Register 27-1: T0CON0: TIMER0 Control Register 0 Register 27-2: T0CON1: TIMER0 Control Register 1 TABLE 27-1: Summary of Registers Associated with Timer0 28.0 Timer1/3/5 Module with Gate Control FIGURE 28-1: Timer1 Block Diagram 28.1 Timer1 Operation TABLE 28-1: Timer1 Enable Selections 28.2 Clock Source Selection 28.2.1 Internal Clock Source 28.2.2 External Clock Source 28.3 Timer Prescaler 28.4 Timer1 16-Bit Read/Write Mode 28.5 Secondary Oscillator 28.6 Timer Operation in Asynchronous Counter Mode 28.6.1 Reading and Writing Timer1 in Asynchronous Counter Mode 28.7 Timer Gate 28.7.1 Timer Gate Enable TABLE 28-2: Timer Gate Enable Selections 28.7.2 Timer Gate Source Selection 28.7.2.1 T1G Pin Gate Operation 28.7.2.2 Timer0 Overflow Gate Operation 28.7.2.3 Comparator C1 Gate Operation 28.7.2.4 Comparator C2 Gate Operation 28.7.3 Timer1 Gate Toggle Mode 28.7.4 Timer1 Gate Single-Pulse Mode 28.7.5 Timer1 Gate Value Status 28.7.6 Timer1 Gate Event Interrupt 28.8 Timer1 Interrupts 28.9 Timer1 Operation During Sleep 28.10 CCP Capture/Compare Time Base 28.11 CCP Auto-Conversion Trigger FIGURE 28-2: Timer1 Incrementing Edge FIGURE 28-3: Timer1 Gate Enable Mode FIGURE 28-4: Timer1 Gate Toggle Mode FIGURE 28-5: Timer1 Gate Single-Pulse Mode FIGURE 28-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 28.12 Register Definitions: Timer1 Control start here with Memory chapter compare TABLE 28-3: Register 28-1: TxCON: Timer1/3/5 Control Register Register 28-2: TxGCON: Timer1/3/5 Gate Control Register Register 28-3: TxCLK Timer1/3/5 Clock Select Register Register 28-4: TxGATE Timer1/3/5 Gate Select Register TABLE 28-4: Summary of Registers Associated with Timer1 29.0 Timer2/4/6 Module FIGURE 29-1: Timer2 Block Diagram FIGURE 29-2: Timer2 Clock Source Block Diagram 29.1 Timer2 Operation 29.1.1 Free Running Period Mode 29.1.2 One-Shot Mode 29.1.3 Monostable Mode 29.2 Timer2 Output 29.3 External Reset Sources TABLE 29-1: Timer2 Operating Modes 29.4 Timer2 Interrupt FIGURE 29-3: Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram 29.5 Operation Examples 29.5.1 Software Gate Mode FIGURE 29-4: Software Gate Mode Timing Diagram (MODE = 00000) 29.5.2 Hardware Gate Mode FIGURE 29-5: Hardware Gate Mode Timing Diagram (MODE = 00001) 29.5.3 Edge-Triggered Hardware Limit Mode FIGURE 29-6: Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) 29.5.4 Level-Triggered Hardware Limit Mode FIGURE 29-7: Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) 29.5.5 Software Start One-Shot Mode FIGURE 29-8: Software Start One-shot Mode Timing Diagram (MODE = 01000) 29.5.6 Edge-Triggered One-Shot Mode FIGURE 29-9: Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) 29.5.7 Edge-Triggered Hardware Limit One-Shot Mode FIGURE 29-10: Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) 29.5.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes FIGURE 29-11: Low Level Reset, Edge-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 01110) 29.5.9 Edge-Triggered Monostable Modes FIGURE 29-12: Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) 29.5.10 Level-Triggered Hardware Limit One-Shot Modes FIGURE 29-13: Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) 29.6 Timer2 Operation During Sleep 29.7 Register Definitions: Timer2/4/6 Control TABLE 29-2: Register 29-1: TxCLKCON: Timer2/4/6 Clock Selection Register Register 29-2: TxCON: Timer2/4/6 Control Register Register 29-3: TxHLT: Timerx Hardware Limit Control Register Register 29-4: TxRST: Timer2/4/6 External Reset Signal Selection Register TABLE 29-3: Summary of Registers Associated with Timer2 30.0 Capture/Compare/PWM Modules TABLE 30-1: Available CCP Modules 30.1 Capture Mode 30.1.1 CAPTURE SOURCES FIGURE 30-1: Capture Mode Operation Block Diagram 30.1.2 Timer1 Mode Resource 30.1.3 Software Interrupt Mode 30.1.4 CCP Prescaler EXAMPLE 30-1: Changing Between Capture Prescalers 30.1.5 Capture During Sleep 30.2 Compare Mode FIGURE 30-2: Compare Mode Operation Block Diagram 30.2.1 CCPx Pin Configuration 30.2.2 Timer1 Mode Resource 30.2.3 Auto-Conversion Trigger 30.2.4 Compare During Sleep 30.3 PWM Overview 30.3.1 Standard PWM Operation FIGURE 30-3: CCP PWM Output Signal FIGURE 30-4: Simplified PWM Block Diagram 30.3.2 Setup for PWM Operation 30.3.3 CCP/PWM Clock Selection 30.3.4 Timer2 Timer Resource 30.3.5 PWM Period EQUATION 30-1: PWM Period 30.3.6 PWM Duty Cycle FIGURE 30-5: PWM 10-Bit Alignment EQUATION 30-2: Pulse Width EQUATION 30-3: Duty Cycle Ratio 30.3.7 PWM Resolution EQUATION 30-4: PWM Resolution TABLE 30-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 30-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 30.3.8 Operation in Sleep Mode 30.3.9 Changes in System Clock Frequency 30.3.10 Effects of Reset 30.4 Register Definitions: CCP Control TABLE 30-4: Long Bit Names Prefixes for CCP Peripherals Register 30-1: CCPXCON: CCPx Control Register Register 30-2: CCPXCAP: Capture Input Selection Register Register 30-3: CCPRXL Register: CCPX Register Low Byte Register 30-4: CCPRXH Register: CCPX Register High Byte Register 30-5: CCPTMRS0: CCP Timers Control 0 Register Register 30-6: CCPTMRS1: CCP Timers Control 1 Register TABLE 30-5: Summary Of Registers Associated with CCPx 31.0 Master Synchronous Serial Port (MSSP) Modules 31.1 MSSP Module Overview FIGURE 31-1: MSSP Block Diagram (SPI mode) FIGURE 31-2: MSSP Block Diagram (I2C Master mode) FIGURE 31-3: MSSP Block Diagram (I2C Slave mode) 31.2 SPI Mode Overview FIGURE 31-4: SPI Master and Multiple Slave Connection 31.2.1 SPI Mode Registers 31.2.2 SPI Mode Operation FIGURE 31-5: SPI Master/Slave Connection 31.2.3 SPI Master Mode FIGURE 31-6: SPI Mode Waveform (Master Mode) 31.2.4 SPI Slave Mode 31.2.4.1 Daisy-Chain Configuration 31.2.5 Slave Select Synchronization FIGURE 31-7: SPI Daisy-Chain Connection FIGURE 31-8: Slave Select Synchronous Waveform FIGURE 31-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 31-10: SPI Mode Waveform (Slave Mode with CKE = 1) 31.2.6 SPI Operation in Sleep Mode 31.3 I2C Mode Overview FIGURE 31-11: I2C Master/ Slave Connection 31.3.1 Clock Stretching 31.3.2 Arbitration 31.4 I2C Mode Operation 31.4.1 Byte Format 31.4.2 Definition of I2C Terminology 31.4.3 SDA and SCL Pins 31.4.4 SDA Hold Time TABLE 31-1: I2C Bus terms 31.4.5 Start Condition 31.4.6 Stop Condition 31.4.7 Restart Condition 31.4.8 Start/Stop Condition Interrupt masking FIGURE 31-12: I2C Start and Stop Conditions FIGURE 31-13: I2C Restart Condition 31.4.9 Acknowledge Sequence 31.5 I2C Slave Mode Operation 31.5.1 Slave Mode Addresses 31.5.1.1 I2C Slave 7-bit Addressing Mode 31.5.1.2 I2C Slave 10-bit Addressing Mode 31.5.2 Slave Reception 31.5.2.1 7-bit Addressing Reception 31.5.2.2 7-bit Reception with AHEN and DHEN FIGURE 31-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 31-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 31-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 31-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 31.5.3 Slave Transmission 31.5.3.1 Slave Mode Bus Collision 31.5.3.2 7-bit Transmission FIGURE 31-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) 31.5.3.3 7-bit Transmission with Address Hold Enabled FIGURE 31-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) 31.5.4 Slave Mode 10-bit Address Reception 31.5.5 10-bit Addressing with Address or Data Hold FIGURE 31-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 31-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 31-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 31.5.6 Clock Stretching 31.5.6.1 Normal Clock Stretching 31.5.6.2 10-bit Addressing Mode 31.5.6.3 Byte NACKing 31.5.7 Clock Synchronization and the CKP bit FIGURE 31-23: Clock Synchronization Timing 31.5.8 General Call Address Support FIGURE 31-24: Slave Mode General Call Address Sequence 31.5.9 SSP Mask Register 31.6 I2C Master Mode 31.6.1 I2C Master Mode Operation 31.6.2 Clock Arbitration FIGURE 31-25: Baud Rate Generator Timing with Clock Arbitration 31.6.3 WCOL Status Flag 31.6.4 I2C Master Mode Start Condition Timing FIGURE 31-26: First Start Bit Timing 31.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 31-27: Repeated Start Condition Waveform 31.6.6 I2C Master Mode Transmission 31.6.6.1 BF Status Flag 31.6.6.2 WCOL Status Flag 31.6.6.3 ACKSTAT Status Flag 31.6.6.4 Typical transmit sequence: FIGURE 31-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) 31.6.7 I2C Master Mode Reception 31.6.7.1 BF Status Flag 31.6.7.2 SSPOV Status Flag 31.6.7.3 WCOL Status Flag 31.6.7.4 Typical Receive Sequence: FIGURE 31-29: I2C Master Mode Waveform (Reception, 7-bit Address) 31.6.8 Acknowledge Sequence Timing 31.6.8.1 WCOL Status Flag 31.6.9 Stop Condition Timing 31.6.9.1 WCOL Status Flag FIGURE 31-30: Acknowledge Sequence Waveform FIGURE 31-31: Stop Condition Receive or Transmit Mode 31.6.10 Sleep Operation 31.6.11 Effects of a Reset 31.6.12 Multi-Master Mode 31.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 31-32: Bus Collision Timing for Transmit and Acknowledge 31.6.13.1 Bus Collision During a Start Condition FIGURE 31-33: Bus Collision During Start Condition (SDA Only) FIGURE 31-34: Bus Collision During Start Condition (SCL = 0) FIGURE 31-35: BRG Reset Due to SDA Arbitration During Start Condition 31.6.13.2 Bus Collision During a Repeated Start Condition FIGURE 31-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 31-37: Bus Collision During Repeated Start Condition (Case 2) 31.6.13.3 Bus Collision During a Stop Condition FIGURE 31-38: Bus Collision During a Stop Condition (Case 1) FIGURE 31-39: Bus Collision During a Stop Condition (Case 2) 31.7 Baud Rate Generator FIGURE 31-40: Baud Rate Generator Block Diagram TABLE 31-2: MSSP Clock Rate w/BRG 31.8 Register Definitions: MSSPx Control Register 31-1: SSPxSTAT: SSPx STATUS Register Register 31-2: SSPxCON1: SSPx Control Register 1 Register 31-3: SSPxCON2: SSPx Control Register 2 (I2C Mode Only)(1) Register 31-4: SSPxCON3: SSPx Control Register 3 Register 31-5: SSPxMSK: SSPx Mask Register Register 31-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode) Register 31-7: SSPxBUF: MSSPx Buffer Register TABLE 31-3: Summary of Registers Associated with MSSPX 32.0 Signal Measurement Timer (SMT) FIGURE 32-1: SMT Block Diagram FIGURE 32-2: SMT Signal and Window Block Diagram 32.1 SMT Operation 32.1.1 Clock Sources 32.1.2 Period Match interrupt 32.2 Basic Timer Function Registers 32.2.1 Time Base 32.2.2 Pulse Width Latch registers 32.2.3 Period Latch registers 32.3 Halt Operation 32.4 Polarity Control 32.5 Status Information 32.5.1 Window Status 32.5.2 Signal Status 32.5.3 GO Status 32.6 Modes of Operation 32.6.1 Timer Mode TABLE 32-1: Modes of Operation FIGURE 32-3: Timer Mode Timing Diagram 32.6.2 Gated Timer Mode FIGURE 32-4: Gated Timer Mode Repeat Acquisition Timing Diagram FIGURE 32-5: Gated Timer Mode Single Acquisition Timing Diagram 32.6.3 Period and Duty-Cycle Mode FIGURE 32-6: Period And Duty-Cycle Repeat Acquisition Mode Timing Diagram FIGURE 32-7: Period And Duty-Cycle Single Acquisition Timing Diagram 32.6.4 High and Low Measure Mode FIGURE 32-8: High and Low Measure Mode Repeat Acquisition Timing Diagram FIGURE 32-9: High and Low Measure Mode Single Acquisition Timing Diagram 32.6.5 Windowed Measure Mode FIGURE 32-10: Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 32-11: Windowed Measure Mode Single Acquisition Timing Diagram 32.6.6 Gated Window Measure Mode FIGURE 32-12: Gated Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 32-13: Gated Windowed Measure Mode Single Acquisition Timing Diagrams 32.6.7 Time of Flight Measure Mode FIGURE 32-14: Time Of Flight Mode Repeat Acquisition Timing Diagram FIGURE 32-15: Time Of Flight Mode Single Acquisition Timing Diagram 32.6.8 Capture Mode FIGURE 32-16: Capture Mode Repeat Acquisition Timing Diagram FIGURE 32-17: Capture Mode Single Acquisition Timing Diagram 32.6.9 Counter Mode FIGURE 32-18: Counter Mode Timing Diagram 32.6.10 Gated Counter Mode FIGURE 32-19: Gated Counter Mode Repeat Acquisition Timing Diagram FIGURE 32-20: Gated Counter Mode Single Acquisition Timing Diagram 32.6.11 Windowed Counter Mode FIGURE 32-21: Windowed Counter Mode Repeat Acquisition Timing Diagram FIGURE 32-22: Windowed Counter Mode Single Acquisition Timing Diagram 32.7 Interrupts 32.7.1 PW and PR Acquisition interrupts 32.7.2 Counter Period Match interrupt 32.8 Register Definitions: SMT Control TABLE 32-2: Long Bit Names Prefixes for SMT Peripherals Register 32-1: SMTxCON0: SMT Control Register 0 Register 32-2: SMTxCON1: SMT Control Register 1 Register 32-3: SMTxSTAT: SMT Status Register Register 32-4: SMTxCLK: SMT Clock Selection Register Register 32-5: SMTxWIN: SMT1 Window Input Select Register Register 32-6: SMTxSIG: SMT1 Signal Input Select Register Register 32-7: SMTxTMRL: SMT Timer Register – Low Byte Register 32-8: SMTxTMRH: SMT Timer Register – High Byte Register 32-9: SMTxTMRU: SMT Timer Register – Upper Byte Register 32-10: SMTxCPRL: SMT Captured Period Register – Low Byte Register 32-11: SMTxCPRH: SMT Captured Period Register – High Byte Register 32-12: SMTxCPRU: SMT Captured Period Register – Upper Byte Register 32-13: SMTxCPWL: SMT Captured Pulse Width Register – Low Byte Register 32-14: SMTxCPWH: SMT Captured Pulse Width Register – High Byte Register 32-15: SMTxCPWU: SMT Captured Pulse Width Register – Upper Byte Register 32-16: SMTxPRL: SMT Period Register – Low Byte Register 32-17: SMTxPRH: SMT Period Register – High Byte Register 32-18: SMTxPRU: SMT Period Register – Upper Byte TABLE 32-3: Summary of Registers Associated with SMTx 33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 33-1: EUSART Transmit Block Diagram FIGURE 33-2: EUSART Receive Block Diagram 33.1 EUSART Asynchronous Mode 33.1.1 EUSART Asynchronous Transmitter 33.1.1.1 Enabling the Transmitter 33.1.1.2 Transmitting Data 33.1.1.3 Transmit Data Polarity 33.1.1.4 Transmit Interrupt Flag 33.1.1.5 TSR Status 33.1.1.6 Transmitting 9-Bit Characters 33.1.1.7 Asynchronous Transmission Set-up: FIGURE 33-3: Asynchronous Transmission FIGURE 33-4: Asynchronous Transmission (Back-to-Back) 33.1.2 EUSART Asynchronous Receiver 33.1.2.1 Enabling the Receiver 33.1.2.2 Receiving Data 33.1.2.3 Receive Interrupts 33.1.2.4 Receive Framing Error 33.1.2.5 Receive Overrun Error 33.1.2.6 Receiving 9-Bit Characters 33.1.2.7 Address Detection 33.1.2.8 Asynchronous Reception Setup: 33.1.2.9 9-bit Address Detection Mode Setup FIGURE 33-5: Asynchronous Reception 33.2 Clock Accuracy with Asynchronous Operation 33.3 EUSART Baud Rate Generator (BRG) EXAMPLE 33-1: Calculating Baud Rate Error 33.3.1 Auto-Baud Detect TABLE 33-1: BRG Counter Clock Rates FIGURE 33-6: Automatic Baud Rate Calibration 33.3.2 Auto-Baud Overflow 33.3.3 Auto-Wake-up on Break 33.3.3.1 Special Considerations FIGURE 33-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 33-8: Auto-Wake-up Bit (WUE) Timings During Sleep 33.3.4 Break Character Sequence 33.3.4.1 Break and Sync Transmit Sequence 33.3.5 Receiving a Break Character FIGURE 33-9: Send Break Character Sequence 33.4 EUSART Synchronous Mode 33.4.1 Synchronous Master Mode 33.4.1.1 Master Clock 33.4.1.2 Clock Polarity 33.4.1.3 Synchronous Master Transmission 33.4.1.4 Synchronous Master Transmission Set-up: FIGURE 33-10: Synchronous Transmission FIGURE 33-11: Synchronous Transmission (Through TXEN) 33.4.1.5 Synchronous Master Reception 33.4.1.6 Slave Clock 33.4.1.7 Receive Overrun Error 33.4.1.8 Receiving 9-bit Characters 33.4.1.9 Synchronous Master Reception Set-up: FIGURE 33-12: Synchronous Reception (Master Mode, SREN) 33.4.2 Synchronous slave Mode 33.4.2.1 EUSART Synchronous Slave Transmit 33.4.2.2 Synchronous Slave Transmission Set-up: 33.4.2.3 EUSART Synchronous Slave Reception 33.4.2.4 Synchronous Slave Reception Set-up: 33.5 EUSART Operation During Sleep 33.5.1 Synchronous Receive During Sleep 33.5.2 Synchronous Transmit During Sleep 33.6 Register Definitions: EUSART Control Register 33-1: TX1STA: Transmit Status and Control Register Register 33-2: RC1STA: Receive Status and Control Register Register 33-3: BAUD1CON: Baud Rate Control Register Register 33-4: RC1REG(1): Receive Data Register Register 33-5: TX1REG(1): Transmit Data Register Register 33-6: SP1BRGL(1): Baud Rate Generator Register Register 33-7: SP1BRGH(1, 2): Baud Rate Generator High Register TABLE 33-2: Summary of Registers Associated with EUSART TABLE 33-3: Baud Rate Formulas TABLE 33-4: Baud Rate For Asynchronous Modes 34.0 Reference Clock Output Module 34.1 CLOCK SOURCE 34.1.1 Clock Synchronization 34.2 PROGRAMMABLE CLOCK DIVIDER 34.3 SELECTABLE DUTY CYCLE 34.4 OPERATION IN SLEEP MODE FIGURE 34-1: Clock Reference Block Diagram FIGURE 34-2: Clock Reference Timing Register 34-1: CLKRCON: Reference Clock Control Register Register 34-2: CLKRCLK: Clock Reference Clock Selection Register TABLE 34-1: Summary of Registers Associated with Clock Reference Output 35.0 In-Circuit Serial Programming™ (ICSP™) 35.1 High-Voltage Programming Entry Mode 35.2 Low-Voltage Programming Entry Mode 35.3 Common Programming Interfaces FIGURE 35-1: ICD RJ-11 Style Connector Interface FIGURE 35-2: PICkit™ Programmer Style Connector Interface FIGURE 35-3: Typical Connection for ICSP™ Programming 36.0 Instruction Set Summary 36.1 Read-Modify-Write Operations TABLE 36-1: Opcode Field Descriptions TABLE 36-2: Abbreviation Descriptions TABLE 36-3: General Format for Instructions TABLE 36-4: Instruction Set TABLE 36-4: Instruction Set (Continued) 36.2 Instruction Descriptions 37.0 Electrical Specifications 37.1 Absolute Maximum Ratings(†) 37.2 Standard Operating Conditions FIGURE 37-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F18855/75 Only FIGURE 37-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF18855/75 Only 37.3 DC Characteristics TABLE 37-1: Supply Voltage FIGURE 37-3: POR and POR Rearm with Slow Rising Vdd TABLE 37-2: Supply Current (Idd)(1,2,4) TABLE 37-3: Power-Down Current (Ipd)(1,2) TABLE 37-4: I/O Ports TABLE 37-5: Memory Programming Specifications TABLE 37-6: Thermal Characteristics 37.4 AC Characteristics FIGURE 37-4: Load Conditions FIGURE 37-5: Clock Timing TABLE 37-7: External Clock/Oscillator Timing Requirements TABLE 37-8: iNTERNAL Oscillator Parameters(1) FIGURE 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 37-9: PLL Specifications FIGURE 37-7: CLKOUT and I/O Timing TABLE 37-10: I/O and CLKOUT Timing Specifications FIGURE 37-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 37-9: Brown-Out Reset Timing and Characteristics TABLE 37-11: Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications TABLE 37-12: Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2): TABLE 37-13: Analog-to-Digital Converter (ADC) Conversion Timing Specifications FIGURE 37-10: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 37-11: ADC Conversion Timing (ADC Clock FRC-based) TABLE 37-14: Comparator Specifications TABLE 37-15: 5-Bit DAC Specifications TABLE 37-16: Fixed Voltage Reference (FVR) Specifications TABLE 37-17: Zero Cross Detect (ZCD) Specifications FIGURE 37-12: Timer0 and Timer1 External Clock Timings TABLE 37-18: Timer0 and Timer1 External Clock Requirements FIGURE 37-13: Capture/Compare/PWM Timings (CCP) TABLE 37-19: Capture/Compare/PWM Requirements (CCP) FIGURE 37-14: CLC Propagation Timing TABLE 37-20: Configurable Logic Cell (CLC) Characteristics FIGURE 37-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 37-21: EUSART Synchronous Transmission Requirements FIGURE 37-16: EUSART Synchronous Receive (Master/Slave) Timing TABLE 37-22: EUSART Synchronous Receive Requirements FIGURE 37-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 37-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 37-19: SPI Slave Mode Timing (CKE = 0) FIGURE 37-20: SPI Slave Mode Timing (CKE = 1) TABLE 37-23: SPI Mode requirements FIGURE 37-21: I2C Bus Start/Stop Bits Timing TABLE 37-24: I2C Bus Start/Stop Bits Requirements FIGURE 37-22: I2C Bus Data Timing TABLE 37-25: I2C Bus Data Requirements 38.0 DC and AC Characteristics Graphs and Charts 39.0 Development Support 39.1 MPLAB X Integrated Development Environment Software 39.2 MPLAB XC Compilers 39.3 MPASM Assembler 39.4 MPLINK Object Linker/ MPLIB Object Librarian 39.5 MPLAB Assembler, Linker and Librarian for Various Device Families 39.6 MPLAB X SIM Software Simulator 39.7 MPLAB REAL ICE In-Circuit Emulator System 39.8 MPLAB ICD 3 In-Circuit Debugger System 39.9 PICkit 3 In-Circuit Debugger/ Programmer 39.10 MPLAB PM3 Device Programmer 39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12 Third-Party Development Tools 40.0 Packaging Information 40.1 Package Marking Information 40.1 Package Marking Information (Continued) 40.1 Package Marking Information (Continued) 40.1 Package Marking Information (Continued) 40.2 Package Details Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales and Service