Product Brief PIC16(L)F1885X/7X (Microchip) - 10
| 制造商 | Microchip |
| 描述 | Full-Featured 28/40-Pin Microcontroller |
| 页数 / 页 | 16 / 10 |
| 文件格式/大小 | PDF / 184 Kb |
| 文件语言 | 英语 |
该数据表的模型线
- PIC16F18857-E/ML PIC16F18857-E/MLVAO PIC16F18857-E/SO PIC16F18857-E/SP PIC16F18857-E/SS PIC16F18857-E/SSVAO PIC16F18857-I/ML PIC16F18857-I/SO PIC16F18857-I/SP PIC16F18857-I/SS PIC16F18857-I/SSVAO PIC16F18857T-E/MLVAO PIC16F18857T-E/SS PIC16F18857T-E/SSVAO PIC16F18857T-I/ML PIC16F18857T-I/SO PIC16F18857T-I/SS PIC16F18857T-I/SSC02 PIC16F18857T-I/SSVAO PIC16LF18857-E/ML PIC16LF18857-E/SO PIC16LF18857-E/SP PIC16LF18857-E/SS PIC16LF18857-I/ML PIC16LF18857-I/SO PIC16LF18857-I/SP PIC16LF18857-I/SS PIC16LF18857T-I/ML PIC16LF18857T-I/SO PIC16LF18857T-I/SS
- PIC16F18877-E/ML PIC16F18877-E/MV PIC16F18877-E/MVVAO PIC16F18877-E/P PIC16F18877-E/PT PIC16F18877-I/ML PIC16F18877-I/MV PIC16F18877-I/P PIC16F18877-I/PREL PIC16F18877-I/PT PIC16F18877T-E/MV PIC16F18877T-E/MVVAO PIC16F18877T-I/ML PIC16F18877T-I/MV PIC16F18877T-I/PT PIC16LF18877-E/ML PIC16LF18877-E/MV PIC16LF18877-E/P PIC16LF18877-E/PT PIC16LF18877-I/ML PIC16LF18877-I/MV PIC16LF18877-I/MVC04 PIC16LF18877-I/P PIC16LF18877-I/PT PIC16LF18877T-I/MV PIC16LF18877T-I/MVC04 PIC16LF18877T-I/PT PIC16LF18877T-I/PTC01 PIC16LF18877T-I/PTRA3
文件文字版本
44-Pin TQFP 40-Pin UQFN 44-Pin QFN ADC Voltage Reference DAC Zero-Cross Detect MSSP (SPI/I2C™) EUSART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic RA0 2 19 17 19 ANA0 — — C1IN0C2IN0-— — — — — — — CLCIN0(1) — — IOCA0 — RA1 3 20 18 20 ANA1 — — C1IN1C2IN1-— — — — — — — CLCIN1(1) — — IOCA1 — RA2 4 21 19 21 ANA2 VREF-DAC1OUT1 C1IN0+
C2IN0+ — — — — — — — — — — IOCA2 — RA3 5 22 20 22 ANA3 VREF+ — C1IN1+ — — — MDCIN1(1) — — — — IOCA3 — (1) Comparators 40-Pin PDIP Advance Information !/O 40/44-PIN ALLOCATION TABLE (PIC16(L)F1887X) — —
(1) 2014 Microchip Technology Inc. RA4 6 23 21 23 ANA4 — — — — — — MDCIN2 — — — — IOCA4 — RA5 7 24 22 24 ANA5 — — — — SS1(1) — MDMIN(1) — — — — — — IOCA5 — RA6 14 31 29 33 ANA6 — — — — — — — — — — — — — IOCA6 OSC2
CLKOUT RA7 13 30 28 32 ANA7 — — — — — — — — — — — — — IOCA7 OSC1
CLKIN RB0 33 8 8 9 ANB0 — — C2IN1+ ZCD SS2(1) — — — CCP4(1) CWG1IN(1) — — — INT(1)
IOCB0 — RB1 34 9 9 10 ANB1 — — C1IN3C2IN3-— SCL2(3,4)
SCK2(1) — — — — CWG2IN(1) — — — IOCB1 — RB2 35 10 10 11 ANB2 — — — — SDA2(3,4)
SDI2(1) — — — — CWG3IN(1) — — — IOCB2 — RB3 36 11 11 12 ANB3 — — C1IN2C2IN2-— — — — — — — — — — IOCB3 — RB4 37 14 12 14 ANB4
ADCACT(1) — — — — — — — T5G(1)
SMTWIN2(1) — — — — — IOCB4 — RB5 38 15 13 15 ANB5 — — — — — — — T1G(1)
SMTSIG2(1) CCP3(1) — — — — IOCB5 — RB6 39 16 14 16 ANB6 — — — — — — — — — — CLCIN2(1) — — IOCB6 ICSPCLK RB7 40 17 15 17 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT Note 1:
2:
3:
4: T0CKI CCP5 (1) This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 5 for details on which PORT pins may
be used for this signal.
All output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 6.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C™ logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but
input logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F1885X/7X DS40001768A-page 10 TABLE 4:
C2IN0+ — — — — — — — — — — IOCA2 — RA3 5 22 20 22 ANA3 VREF+ — C1IN1+ — — — MDCIN1(1) — — — — IOCA3 — (1) Comparators 40-Pin PDIP Advance Information !/O 40/44-PIN ALLOCATION TABLE (PIC16(L)F1887X) — —
(1) 2014 Microchip Technology Inc. RA4 6 23 21 23 ANA4 — — — — — — MDCIN2 — — — — IOCA4 — RA5 7 24 22 24 ANA5 — — — — SS1(1) — MDMIN(1) — — — — — — IOCA5 — RA6 14 31 29 33 ANA6 — — — — — — — — — — — — — IOCA6 OSC2
CLKOUT RA7 13 30 28 32 ANA7 — — — — — — — — — — — — — IOCA7 OSC1
CLKIN RB0 33 8 8 9 ANB0 — — C2IN1+ ZCD SS2(1) — — — CCP4(1) CWG1IN(1) — — — INT(1)
IOCB0 — RB1 34 9 9 10 ANB1 — — C1IN3C2IN3-— SCL2(3,4)
SCK2(1) — — — — CWG2IN(1) — — — IOCB1 — RB2 35 10 10 11 ANB2 — — — — SDA2(3,4)
SDI2(1) — — — — CWG3IN(1) — — — IOCB2 — RB3 36 11 11 12 ANB3 — — C1IN2C2IN2-— — — — — — — — — — IOCB3 — RB4 37 14 12 14 ANB4
ADCACT(1) — — — — — — — T5G(1)
SMTWIN2(1) — — — — — IOCB4 — RB5 38 15 13 15 ANB5 — — — — — — — T1G(1)
SMTSIG2(1) CCP3(1) — — — — IOCB5 — RB6 39 16 14 16 ANB6 — — — — — — — — — — CLCIN2(1) — — IOCB6 ICSPCLK RB7 40 17 15 17 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT Note 1:
2:
3:
4: T0CKI CCP5 (1) This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 5 for details on which PORT pins may
be used for this signal.
All output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 6.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C™ logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but
input logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F1885X/7X DS40001768A-page 10 TABLE 4: