Product Brief PIC16(L)F191XX (Microchip) - 10

 2016
TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F19155/56)
Micr
IC
ochip T
O t e /S c g P n N te a t O e or e h n c MT ) S at D -C rre p
e
n ic (2 /S s /S P C D
ch
P UQF re ar s CC on ll-u s in p rs SSP ADC ro DAC CC CL LC t- Cu u
nol
I/O DI fe PWM CWG M RT h Ba -P m C P Re o ime EUSART up
ogy
SP 28 C ro- T rr Hig n Ze te
I
-Pi In
n
8
c.
2
C1IN0- RA0 2 27 ANA0 — — — — — — — — — CLCIN0
(1)
— SEG0 IOCA0 — Y — C2IN0- C1IN1- RA1 3 28 ANA1 — — — — — — — — — CLCIN1
(1)
— SEG1 IOCA1 — — — C2IN1- C1IN0+ RA2 4 1 ANA2 — — DAC1OUT1 — — — — — — — — SEG2 IOCA2 — Y — C2IN0+ RA3 5 2 ANA3 VREF+ C1IN1+ — DAC1REF+ — — — — — — — — SEG3 IOCA3 — Y — SEG4 RA4 6 3 ANA4 — — — — T0CKI
(1)
— — — — — — — IOCA4 — Y — COM3 RA5 7 4 — — — — — — — — — SS
(1)
— — — — IOCA5 — Y VBAT CLKOUT RA6 10 7 ANA6 — — — — — — — — — — — — SEG6 IOCA6 — Y OSC2 OSC1 RA7 9 6 ANA7 — — — — — — — — — — — — SEG7 IOCA7 — Y CLKIN RB0 21 18 ANB0 — C2IN1+ ZCD — — — — CWG1IN
(1)
— — — — SEG8 IOCB0 — Y INTPPS C1IN3- SCL, RB1 22 19 ANB1 — — — — — — — C2IN3- SDA
(1, 3, 4, 5, 6)
— — — SEG9 IOCB1 HIB1 Y — SEG10 SCL,
PIC16(L)F191XX
RB2 23 20 ANB2 — — — — — — — — COM7 IOCB2 — Y — SDA
(1, 3, 4, 5, 6)
— — — VLCAP1 SEG11 C1IN2- RB3 24 21 ANB3 — — — — — — — — — — — COM6 IOCB3 — Y — C2IN2- VLCAP2 ANB4 RB4 25 22 ADCACT
(1)
— — — — — — — — — — — — COM0 IOCB4 — Y — SEG13 DS RB5 26 23 ANB5 — — — — T1G
(1)
— — — — — — — IOCB5 — Y — COM1 40001863A
Note 1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2:
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by INLCVL register, instead of the I2C specific or SMBUS input buffer thresholds. -page 10
5:
These are alternative I2C logic levels pins.
6:
In I2C logic levels configuration, these pins can operate as either SCL and SDA pins. Document Outline Description: Core Features: Memory: Operating Characteristics: Power-Saving Functionality: eXtreme Low-Power (XLP) Features: Digital Peripherals: Analog Peripherals: Flexible Oscillator Structure: TABLE 1: PIC16(L)F191XX Family Types TABLE 2: Packages Pin Diagrams FIGURE 1: 28-Pin SSOP, SPDIP and SOIC package Diagram for PIC16(L)F19155/56 FIGURE 2: 28-Pin UQFN Package Diagram For PIC16(L)F19155/56 FIGURE 3: 40-Pin PDIP Package Diagram For PIC16(L)F19175/76 FIGURE 4: 40-Pin UQFN (5x5X0.5) Package Diagram For PIC16(L)F19175/76 FIGURE 5: 44-Pin TQFP package Diagram for PIC16(L)F19175/76 FIGURE 6: 44-Pin QFN (8x8X0.9) Package Diagram For PIC16(L)F19175/76 FIGURE 7: 48-Pin TQFP/UQFN package Diagram for PIC16(L)F19185/86 FIGURE 8: 64-Pin TQFP/QFN package Diagram for PIC16(L)F19195/96/97 TABLE 3: 28-Pin Allocation Table (PIC16(L)F19155/56) TABLE 4: 40/44-Pin Allocation Table (PIC16(L)F19175/76) TABLE 5: 48-Pin Allocation Table (PIC16(L)F19185/86) TABLE 6: 64-Pin Allocation Table (PIC16(L)F19195/96/97) Trademarks Worldwide Sales