Product Brief PIC18FXXQ84 (Microchip) - 9
| 制造商 | Microchip |
| 描述 | Microcontrollers in 28/40/44/48-pin devices for many automotive and industrial application |
| 页数 / 页 | 20 / 9 — PIC18FXXQ84. Pin Diagrams. Figure 2-3. 40-Pin PDIP. Figure 2-4. 40-Pin, … |
| 文件格式/大小 | PDF / 331 Kb |
| 文件语言 | 英语 |
PIC18FXXQ84. Pin Diagrams. Figure 2-3. 40-Pin PDIP. Figure 2-4. 40-Pin, VQFN. Note: . Product Brief
该数据表的模型线
文件文字版本
Filename: 00-000040A.vsd Title: 40-pin DIP Last Edit: 10/3/2018
PIC18FXXQ84
First Used: N/A Notes: Generic 40-pin dual in-line diagram
Pin Diagrams Figure 2-3. 40-Pin PDIP
Rev. 00-000040A 10/3/2018 MCLR/VPP/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 Filename: 00-000040B.vsd RC2 Title: 40-pin QFN 17 24 RC5 Last Edit: 11/6/2017 RC3 18 23 RC4 First Used: N/A RD0 19 22 RD3 Notes: Generic 40-pin QFN diagram RD1 20 21 RD2
Figure 2-4. 40-Pin, VQFN
Rev. 00-000040B 11/6/2017 6 5 4 3 2 1 0 3 2 1 C C C D D D D C C C R R R R R R R R R R 40 39 38 37 36 35 34 33 32 31 RC7 1 30 RC0 RD4 2 29 RA6 RD5 3 28 RA7 RD6 4 27 VSS RD7 5 26 VDD VSS 6 25 RE2 VDD 7 24 RE1 RB0 8 23 RE0 RB1 9 22 RA5 RB2 10 21 RA4 11 12 13 14 15 16 17 18 19 20 3 4 5 6 7 3 0 1 2 3 B B B B B E A A A A R R R R R R R /R /R /R T LK A LR C D C P P S /M S P IC P IC V
Note:
It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. © 2019 Microchip Technology Inc.
Product Brief
DS40002148A-page 9 Document Outline Introduction PIC18 Q84 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
PIC18FXXQ84
First Used: N/A Notes: Generic 40-pin dual in-line diagram
Pin Diagrams Figure 2-3. 40-Pin PDIP
Rev. 00-000040A 10/3/2018 MCLR/VPP/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 Filename: 00-000040B.vsd RC2 Title: 40-pin QFN 17 24 RC5 Last Edit: 11/6/2017 RC3 18 23 RC4 First Used: N/A RD0 19 22 RD3 Notes: Generic 40-pin QFN diagram RD1 20 21 RD2
Figure 2-4. 40-Pin, VQFN
Rev. 00-000040B 11/6/2017 6 5 4 3 2 1 0 3 2 1 C C C D D D D C C C R R R R R R R R R R 40 39 38 37 36 35 34 33 32 31 RC7 1 30 RC0 RD4 2 29 RA6 RD5 3 28 RA7 RD6 4 27 VSS RD7 5 26 VDD VSS 6 25 RE2 VDD 7 24 RE1 RB0 8 23 RE0 RB1 9 22 RA5 RB2 10 21 RA4 11 12 13 14 15 16 17 18 19 20 3 4 5 6 7 3 0 1 2 3 B B B B B E A A A A R R R R R R R /R /R /R T LK A LR C D C P P S /M S P IC P IC V
Note:
It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. © 2019 Microchip Technology Inc.
Product Brief
DS40002148A-page 9 Document Outline Introduction PIC18 Q84 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service