Datasheet PIC18(L)F2X/4X/5XK42 (Microchip) - 9

 2016
PIN ALLOCATION TABLES
Micr
TABLE 3: 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42)
ochip T e ch
P ) R t
nol
e ge /SSO c c LK N n n rs te M a
ogy
IC F e (C h O re e )Q MT fe to D /S C PW e C ra s C RT /S d G C nc n-C
I
I/O IP (U a p 2 I SPI rs n re asic
n
in AD e R DA ros UA DSM CW CL NCO fe t-o B
c.
m -P C me e up SPD Ti 28 ltag Co ro R rr in o CCP a k V Ze te -P In 8 loc 2 C A
RA0 2 27 ANA0 — — C1IN0- — — — — — — — — CLCIN0
(1)
— — IOCA0 — C2IN0-
d va
RA1 3 28 ANA1 — — C1IN1- — — — — — — — — CLCIN1
(1)
— — IOCA1 — C2IN1-
nce Inf
RA2 4 1 ANA2 VREF- DAC1OUT1 C1IN0+ — — — — — — — — — — — IOCA2 — C2IN0+ RA3 5 2 ANA3 VREF+ — C1IN1+ — — — — MDCARL
(1)
— — — — — — IOCA3 — RA4 6 3 ANA4 — — — — — — — MDCARH
(1)
T0CKI
(1)
— — — — — IOCA4 —
PIC18(L)F2X/4X/5XK42 o r
RA5 7 4 ANA5 — — — — — SS1
(1)
— MDSRC
(1)
— — — — — — IOCA5 —
m
RA6 10 7 ANA6 — — — — — — — — — — — — — — IOCA6 OSC2
at
CLKOUT
ion
RA7 9 6 ANA7 — — — — — — — — — — — — — — IOCA7 OSC1 CLKIN RB0 21 18 ANB0 — — C2IN1+ ZCD — — — — — CCP4
(1)
CWG1IN
(1)
— — — INT0
(1)
— IOCB0 RB1 22 19 ANB1 — — C1IN3- — SCL2
(3,4)
— — — — — CWG2IN
(1)
— — — INT1
(1)
— C2IN3- IOCB1 RB2 23 20 ANB2 — — — — SDA2
(3,4)
— — — — — CWG3IN
(1)
— — — INT2
(1)
— IOCB2 RB3 24 21 ANB3 — — C1IN2- — — — — — — — — — — — IOCB3 — C2IN2- RB4 25 22 ANB4 — — — — — — — — T5G
(1)
— — — — — IOCB4 — ADCACT
(1)
RB5 26 23 ANB5 — — — — — — — — T1G
(1)
CCP3
(1)
— — — — IOCB5 — DS RB6 27 24 ANB6 — — — — — — CTS2
(1)
— — — — CLCIN2
(1)
— — IOCB6 ICSPCLK 40001861B RB7 28 25 ANB7 — DAC1OUT2 — — — — RX2
(1)
— T6IN(1) — — CLCIN3
(1)
— — IOCB7 ICSPDAT
Note 1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2:
All output signals shown in this row are PPS remappable.
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. -page 9
4:
These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales