Datasheet MAX517, MAX518, MAX519 (Maxim) - 7
| 制造商 | Maxim |
| 描述 | 2-Wire, Serial, 8-Bit DACs with Rail-to-Rail Outputs |
| 页数 / 页 | 16 / 7 — 2-Wire Serial 8-Bit DACs with. Rail-to-Rail Outputs. MAX517/MAX518/MAX519 |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
2-Wire Serial 8-Bit DACs with. Rail-to-Rail Outputs. MAX517/MAX518/MAX519
该数据表的模型线
- MAX517ACPA MAX517ACPA+ MAX517ACSA MAX517ACSA+ MAX517ACSA+T MAX517AEPA MAX517AEPA+ MAX517AESA MAX517AESA+ MAX517AESA+T MAX517BCPA MAX517BCPA+ MAX517BCSA MAX517BCSA+ MAX517BCSA+T MAX517BEPA MAX517BEPA+ MAX517BESA MAX517BESA+ MAX517BESA+T
文件文字版本
2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX517/MAX518/MAX519 ______________________________________________________________Pin Description PIN NAME FUNCTION MAX517 MAX518 MAX519
1 1 1 OUT0 DAC0 Voltage Output 2 2 4 GND Ground — — 5 AD3 Address Input 3; sets IC’s slave address 3 3 6 SCL Serial Clock Input 4 4 8 SDA Serial Data Input — — 9 AD2 Address Input 2; sets IC’s slave address 5 5 10 AD1 Address Input 1; sets IC’s slave address 6 6 11 AD0 Address Input 0; sets IC’s slave address 7 7 12 VDD Power Supply, +5V; used as reference for MAX518 — — 13 REF1 Reference Voltage Input for DAC1 8 — 15 REF0 Reference Voltage Input for DAC0 — 8 16 OUT1 DAC1 Voltage Output — — 2, 3, 7, 14 N.C. No Connect—not internally connected.
_______________Detailed Description
VDD REF0 (REF1)
Serial Interface
The MAX517/MAX518/MAX519 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (µP) port. Figure 2 shows INPUT OUTPUT DAC0 LATCH 0 LATCH 0 OUT0 the timing diagram for signals on the 2-wire bus. Figure 3 shows a typical application. The 2-wire bus can have several devices (in addition to the MAX517/ MAX518/MAX519) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in INPUT OUTPUT DAC1 (OUT1) use, the port bits are toggled to generate the appropriate LATCH 1 LATCH 1 signals for SDA and SCL. External pull-up resistors are MAX519 ONLY not required on these lines. The MAX517/MAX518/ MAX519 can be used in applications where pull-up resis- tors are required (such as in I2C systems) to maintain 8-BIT ADDRESS SHIFT compatibility with existing circuitry. COMPARATOR REGISTER The MAX517/MAX518/MAX519 are receive-only devices MAX517/MAX519 SCL and must be controlled by a bus master device. They SDA operate at SCL rates up to 400kHz. A master device sends information to the devices by transmitting their START/STOP DECODE DETECTOR address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX517/MAX518/MAX519’s programm- AD0 (AD2) GND able slave-address, one or more command-byte/out- AD1 (AD3) put-byte pairs (or a command byte alone, if it is the last ( ) ARE FOR MAX519 byte in the transmission), and finally, a STOP condition (Figure 4). Figure 1. MAX517/MAX519 Functional Diagram
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1 1 1 OUT0 DAC0 Voltage Output 2 2 4 GND Ground — — 5 AD3 Address Input 3; sets IC’s slave address 3 3 6 SCL Serial Clock Input 4 4 8 SDA Serial Data Input — — 9 AD2 Address Input 2; sets IC’s slave address 5 5 10 AD1 Address Input 1; sets IC’s slave address 6 6 11 AD0 Address Input 0; sets IC’s slave address 7 7 12 VDD Power Supply, +5V; used as reference for MAX518 — — 13 REF1 Reference Voltage Input for DAC1 8 — 15 REF0 Reference Voltage Input for DAC0 — 8 16 OUT1 DAC1 Voltage Output — — 2, 3, 7, 14 N.C. No Connect—not internally connected.
_______________Detailed Description
VDD REF0 (REF1)
Serial Interface
The MAX517/MAX518/MAX519 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (µP) port. Figure 2 shows INPUT OUTPUT DAC0 LATCH 0 LATCH 0 OUT0 the timing diagram for signals on the 2-wire bus. Figure 3 shows a typical application. The 2-wire bus can have several devices (in addition to the MAX517/ MAX518/MAX519) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in INPUT OUTPUT DAC1 (OUT1) use, the port bits are toggled to generate the appropriate LATCH 1 LATCH 1 signals for SDA and SCL. External pull-up resistors are MAX519 ONLY not required on these lines. The MAX517/MAX518/ MAX519 can be used in applications where pull-up resis- tors are required (such as in I2C systems) to maintain 8-BIT ADDRESS SHIFT compatibility with existing circuitry. COMPARATOR REGISTER The MAX517/MAX518/MAX519 are receive-only devices MAX517/MAX519 SCL and must be controlled by a bus master device. They SDA operate at SCL rates up to 400kHz. A master device sends information to the devices by transmitting their START/STOP DECODE DETECTOR address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX517/MAX518/MAX519’s programm- AD0 (AD2) GND able slave-address, one or more command-byte/out- AD1 (AD3) put-byte pairs (or a command byte alone, if it is the last ( ) ARE FOR MAX519 byte in the transmission), and finally, a STOP condition (Figure 4). Figure 1. MAX517/MAX519 Functional Diagram
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