Datasheet SIC466, SiC467, SiC468, SiC469 (Vishay) - 2
| 制造商 | Vishay |
| 描述 | 4.5 V to 60 V Input, 2 A, 4 A, 6 A, 10 A microBUCK DC/DC Converter |
| 页数 / 页 | 24 / 2 — SiC466, SiC467, SiC468, SiC469. PIN CONFIGURATION. Fig. 3 - Pin … |
| 文件格式/大小 | PDF / 955 Kb |
| 文件语言 | 英语 |
SiC466, SiC467, SiC468, SiC469. PIN CONFIGURATION. Fig. 3 - Pin Configuration. PIN DESCRIPTION. PIN NUMBER. SYMBOL. DESCRIPTION
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文件文字版本
SiC466, SiC467, SiC468, SiC469
www.vishay.com Vishay Siliconix
PIN CONFIGURATION
ND W ND DD G FB OUT OUT FB G W DD MODE V I LIM f S A V V V V A f S I LIM V 27 26 25 24 23 22 21 NC 20 20 21 NC 22 23 24 25 26 27 MODE V IJ CIN 1 19 SS SS 19 1 VCIN PGOOD 2 28 AGND 18 NC NC 1 8 28 AGND 2 PGOOD 17 P P 1 7 GND GND EN 3 3 EN 16 V V 1 6 DRV DRV BOOT 4 15 GL GL 1 5 4 BOOT 30 14 SW SW 1 4 PHASE 5 VIN 29 29 PGND 5 PHASE 13 SW SW 1 3 30 P V GND IN PHASE 6 ķ ķ 6 PHASE 12 SW SW 1 2 9 7 8 9 8 7 11 10 10 11 IN IN ND ND ND IN IN V ND ND ND V G G G V V G G G P P P P P P
Fig. 3 - Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
Supply voltage for internal regulators V 1 V DD and VDRV. This pin should be tied to VIN, but can also be CIN connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators Open-drain power good indicator - high impedance indicates power is good. An external pull-up 2 PGOOD resistor is required Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin, 3 EN can be tied to 60 V 4 BOOT High side driver bootstrap voltage 5, 6 PHASE Return path of high side gate driver 7, 8, 29 VIN Power stage input voltage. Drain of high side MOSFET 9, 10, 11, 17, 30 PGND Power ground 12, 13, 14 SW Power stage switch node 15 GL Low side MOSFET gate signal Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V 16 V DRV is DRV the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18, 21 NC No connection internally Set the soft start ramp by connecting a capacitor to A 19 SS GND. An internal current source will charge the capacitor 20 VOUT Output voltage sense point for internal ripple injection components Feedback input for switching regulator used to program the output voltage - connect to an external 22 VFB resistor divider from VOUT to AGND 23, 28 AGND Analog ground 24 fSW Set the on-time by connecting a resistor to AGND 25 ILIMIT Set the current limit by connecting ILIMIT pin to AGND, float or VDD 26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND 27 Mode Set various operation modes by connecting a resistor to AGND. See specification table for details S19-0911-Rev. E, 28-Oct-2019
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Document Number: 76044 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
PIN CONFIGURATION
ND W ND DD G FB OUT OUT FB G W DD MODE V I LIM f S A V V V V A f S I LIM V 27 26 25 24 23 22 21 NC 20 20 21 NC 22 23 24 25 26 27 MODE V IJ CIN 1 19 SS SS 19 1 VCIN PGOOD 2 28 AGND 18 NC NC 1 8 28 AGND 2 PGOOD 17 P P 1 7 GND GND EN 3 3 EN 16 V V 1 6 DRV DRV BOOT 4 15 GL GL 1 5 4 BOOT 30 14 SW SW 1 4 PHASE 5 VIN 29 29 PGND 5 PHASE 13 SW SW 1 3 30 P V GND IN PHASE 6 ķ ķ 6 PHASE 12 SW SW 1 2 9 7 8 9 8 7 11 10 10 11 IN IN ND ND ND IN IN V ND ND ND V G G G V V G G G P P P P P P
Fig. 3 - Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
Supply voltage for internal regulators V 1 V DD and VDRV. This pin should be tied to VIN, but can also be CIN connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators Open-drain power good indicator - high impedance indicates power is good. An external pull-up 2 PGOOD resistor is required Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin, 3 EN can be tied to 60 V 4 BOOT High side driver bootstrap voltage 5, 6 PHASE Return path of high side gate driver 7, 8, 29 VIN Power stage input voltage. Drain of high side MOSFET 9, 10, 11, 17, 30 PGND Power ground 12, 13, 14 SW Power stage switch node 15 GL Low side MOSFET gate signal Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V 16 V DRV is DRV the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18, 21 NC No connection internally Set the soft start ramp by connecting a capacitor to A 19 SS GND. An internal current source will charge the capacitor 20 VOUT Output voltage sense point for internal ripple injection components Feedback input for switching regulator used to program the output voltage - connect to an external 22 VFB resistor divider from VOUT to AGND 23, 28 AGND Analog ground 24 fSW Set the on-time by connecting a resistor to AGND 25 ILIMIT Set the current limit by connecting ILIMIT pin to AGND, float or VDD 26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND 27 Mode Set various operation modes by connecting a resistor to AGND. See specification table for details S19-0911-Rev. E, 28-Oct-2019
2
Document Number: 76044 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000