Datasheet 48L256 (Microchip) - 2

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48L256 General Description Powering the Device During SRAM to EEPROM Backup (V
The Microchip Technology Inc. 48L256 serial EERAM
CAP)
has an SRAM memory core with hidden EEPROM A small capacitor (typically 33 μF) is required for the backup. The device can be treated by the user as a full proper operation of the device. This capacitor is placed symmetrical read/write SRAM. Backup to EEPROM is between VCAP (pin 3) and the system VSS (see Normal handled by the device on any power disrupt, so the Device Operation). When power is first applied to the user can effectively view this device as an SRAM that device, this capacitor is charged to VCC through the never loses its data. device (see Normal Device Operation). During normal The device is structured as a 256-Kbit SRAM with SRAM operation, the capacitor remains charged to EEPROM backup in each memory cell. The SRAM is VCC and the level of system VCC is monitored by the organized as 32,768 x 8 bits and uses the SPI serial device. If system VCC drops below a set threshold, the interface. The SPI bus uses three signal lines for device interprets this as a power-off or brown-out communication: clock input (SCK), data in (SI), and event. The device suspends all I/O operation, shuts off data out (SO). Access to the device is controlled its connection with the VCC pin, and uses the saved through a Chip Select (CS) input, allowing any number energy in the capacitor to power the device through the of devices to share the same bus. VCAP pin as it transfers all SRAM data to EEPROM (see Vcc Power-Off Event). On the next power-up of The SRAM is a conventional serial SRAM: it allows VCC, the data is transfered back to SRAM, the capaci- symmetrical reads and writes and has no limits on cel tor is recharged, and the SRAM operation continues. usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently.
Normal Device Operation
The device includes circuitry that detects VCC dropping below a certain threshold, shuts its V (pin 8)
System V
connection to the outside environment, and transfers CC
CC
all SRAM data to the EEPROM portion of each cell for V Monitor CC safe keeping. When VCC returns, the circuitry V (pin 3) CAP automatically returns the data to the SRAM and the user’s interaction with the SRAM can continue with the C Charged to V VCAP CC same data set. CS Normal SO SRAM SI
Block Diagram
Operation V (pin 4) SS SCK HOLD VCC Power
System VSS
Control VCAP Block Memory Address
VCC Power-Off Event
and Data Control CS SPI Control Logic Logic SO V (pin 8) CC
System VCC
SI and Address Automatic Decoder SCK Backup V (pin 3) HOLD CAP EEPROM EEPROM C Temporary V SRAM VCAP CC STATUS 32K x 8 CS Register SO SRAM to V (pin 4) SRAM SI EEPROM SS SCK STORE Transfer 32K x 8 HOLD
System V
RECALL
SS
 2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 2 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service