Datasheet 48L256 (Microchip) - 4

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48L256 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 2.7V to 3.6V
Param. Symbol Characteristic Min. Max. Units Conditions No.
1 FCLK Clock Frequency — 66 MHz 2 TCSS CS Setup Time 6 — ns 3 TCSH CS Hold Time 6 — ns 4 TCSD CS Disable Time 7 — ns 5 TSU Data Setup Time 4 — ns 6 THD Data Hold Time 4 — ns 7 TR CLK Rise Time — 100 ns
Note 1
8 TF CLK Fall Time — 100 ns
Note 1
9 THI Clock High Time 7 — ns 10 TLO Clock Low Time 7 — ns 11 TCLD Clock Delay Time 7 — ns 12 TCLE Clock Enable Time 3 — ns 13 TV Output Valid from Clock Low — 10 ns 14 THO Output Hold Time 0 — ns
Note 1
15 TDIS Output Disable Time — 20 ns
Note 1
16 THZ HOLD Low to Output High-Z — 10 ns
Note 1
17 THV HOLD High to Output Valid — 10 ns 18 THS HOLD Setup Time 0 ns 19 THH HOLD Hold Time 5 ns 20 TRESTORE Power-up AutoRecal /Hibernation — 200 μs Wake-up Operation Duration 21 TRECALL SW Recall Operation Duration — 50 μs 22 TSTORE Store Operation Duration — 10 ms 23 TVRISE VCC Rise Rate 30 — μs/V
Note 1
24 TvFALL VCC Fall Rate 30 — μs/V
Note 1
25 Endurance 100,000 — Store
Note 1
Cycles 26 Retention 100 — Years At 55°C 10 — Years At 85°C
Note 1:
This parameter is not tested but ensured by characterization.  2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 4 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service