Datasheet 48L512, 48LM01 (Microchip) - 3

link to page 3 link to page 3 link to page 3 link to page 3 link to page 3
48L512/48LM01 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings†
VCC...4.5V All inputs and outputs w.r.t. VSS ... -0.6V to 4.5V Storage temperature ...-65°C to +150°C Ambient temperature under bias...-40°C to +85°C ESD protection on all pins.. 2 kV
† NOTICE:
Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 2.7V to 3.6V
Param. Symbol Characteristic Min. Typical Max. Units Conditions No.
D1 VIH High-Level Input VCC x 0.8 — VCC + 0.5 V Voltage D2 VIL Low-Level Input -0.5 — VCC x 0.2 V Voltage D3 VOH High-Level Output VCC - 0.5 — — V IOH = -0.4 mA Voltage D4 VOL Low-Level Output — — 0.4 V IOL = 2.0 mA Voltage D5 ILI Input Leakage Current — — ±3 μA VIN = VSS or VCC D6 ILO Output Leakage — — ±3 μA CS = VCC, VOUT = VSS or VCC Current D7 CIN Internal Capacitance — — 5 pF TA = 25°C, FREQ = 1 MHz, (all input pins) VCC = 3.6V (
Note 1
) D8 COUT Internal Capacitance — — 7 pF TA = 25°C, FREQ = 1 MHz, (SO pin) VCC = 3.6V (
Note 1
) D9 ICC Operating Current — — 5 mA TA = 85°C, VCC = 3.6V, Active FCLK = 66 MHz (
Note 3
) D10 ICC Store Current — — 2 mA TA = 85°C, Store 2.7V < VCC ≤ 3.6V (
Note 2
) D11 ICCS Standby Current — — 200 μA TA = 85°C, SI, CS, VCAP, VCC = 3.6V D12 ICCH Hibernate Current — — 3 μA TA = 85°C, SI, CS, VCAP, VCC = 3.6V D13 VTRIP AutoStore/AutoRecal 2.30 — 2.65 V Trip Voltage D14 VHYS Trip Voltage Hysteresis — 300 — mV
Note 1 Note 1:
This parameter is periodically sampled and not 100% tested.
2:
Store current is specified as an average current across the entire store operation.
3:
ICC Active measured with SO pin unloaded. Current can vary with output loading and clock frequency.  2018-2019 Microchip Technology Inc. DS20006008C-page 3 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L512/48LM01 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Byte Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L512/48LM01 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow FIGURE 11-4: AutoStore/AutoRecall Scenarios (with ASE = 0, Array Modified) FIGURE 11-5: AutoStore/AutoRecall Scenarios (with ASE = 1 or Array Not Modified) 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales