Datasheet 2ED2182 (4) S06F (J) (Infineon) - 6

制造商Infineon
描述650 V half-bridge gate driver with integrated bootstrap diode
页数 / 页24 / 6 — 2ED2182. (4). S06F. (J). 650. V. half-bridge. gate. driver. with. …
修订版02_01
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2ED2182. (4). S06F. (J). 650. V. half-bridge. gate. driver. with. integrated. bootstrap. diode. 4. Electrical. parameters. 4.1. Absolute. maximum. ratings

2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 4 Electrical parameters 4.1 Absolute maximum ratings

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2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 4 Electrical parameters 4.1 Absolute maximum ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and stil air conditions. Table 3 Absolute maximum ratings Symbol Definition Min. Max. Units VB High-side floating wel supply voltage (Note 1) VCC – 5 675 VS High-side floating wel supply return voltage VCC – VBS– 5 650 VHO Floating gate drive output voltage VS – 0.5 VB + 0.5 VCC Low side supply voltage -1 25 VLO Low-side output voltage –0.5 VCC + 0.5 V VIN Logic input voltage (HIN & LIN) -5/ (VSS – 5) VCC + 0.5 Vss Logic ground (2ED21824S06J only) VCC – 25 VCC + 0.5 DT Programmable dead time pin voltage (2ED21824S06J only) VSS – 5 VCC + 0.5 dVS/dt Allowable VS offset supply transient relative to COM — 50 V/ns Package power dissipation — P 8-Lead DSO-8 0.625 D @ T W A ≤+25ºC 14-Lead DSO-14 — 1 — 200 Rth 8-Lead DSO-8 JA Thermal resistance, junction to ambient 14-Lead DSO-14 ºC/W — 120 TJ Junction temperature — 150 TS Storage temperature -55 150 ºC TL Lead temperature (soldering, 10 seconds) — 300 Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VB. 4.2 Recommended operating conditions For proper operation, the device should be used within the recommended conditions. Al voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with supplies of (VCC – COM) = (VB – VS) = 15 V. Table 4 Recommended operating conditions Symbol Definition Min Max Units VB Bootstrap voltage VS + 10 VS + 20 VBS High-side floating well supply voltage 10 20 VS High-side floating well supply offset voltage VCC – VBS– 1 650 VHO Floating gate drive output voltage VS VB VCC Low-side supply voltage 10 20 V V LO Low-side output voltage COM VCC VIN Logic input voltage(HIN & LIN) -4 / (VSS – 4) 5 / (VSS + 5) V Logic ground (2ED21824S06J only) with respect to SS COM -5 +5 DT Programmable dead time pin voltage (2ED21824S06J only) VSS – 4 5 TA Ambient temperature -40 125 ºC Note 2: Logic operation for VS of – 10 V to +650 V. Datasheet 6 of 24 V 2.10 www.infineon.com/soi 2019-09-12 Document Outline Features Product summary Product validation Description Summary of feature comparison of the 2ED218x family 1 Table of contents 2 Block diagram 3 Pin configuration and functionality 3.1 Pin configuration 3.2 Pin functionality 4 Electrical parameters 4.1 Absolute maximum ratings 4.2 Recommended operating conditions 4.3 Static electrical characteristics 4.4 Dynamic electrical characteristics 5 Application information and additional details 5.1 IGBT / MOSFET gate drive 5.2 Switching and timing relationships 5.3 Deadtime and matched propagation delays 5.4 Input logic compatibility 5.5 Undervoltage lockout 5.6 Bootstrap diode 5.7 Calculating the bootstrap capacitance CBS 5.8 Tolerant to negative tranisents on input pins 5.9 Negative voltage transient tolerance of VS pin 5.10 NTSOA – Negative Transient Safe Operating Area 5.11 Higher headroom for input to output signal transmission with logic operation upto -11 V 5.12 Maximum switching frequency 5.13 PCB layout tips 6 Qualification information0F 7 Related products 8 Package details 9 Part marking information 10 Additional documentation and resources 10.1 Infineon online forum resources 11 Revision history