Datasheet 2ED2184 (4) S06F (J) (Infineon) - 10

2ED2184 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 5.3 Deadtime and matched propagation delays This 2ED2184 (4) S06F (J) features integrated deadtime protection circuitry. The deadtime is fixed for 2ED2184S06F; is programmable for 2ED2184S06J, it provides greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatical y inserter whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 8 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of 2ED2184 (4) S06F (J) is matched with respect to the high- and low-side outputs. Figure 9 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT) associated with the 2ED2184S06F (J) specifies the maximum difference between DTLO-HO and DTHO-LO. Figure 8 Dead Time Definitions Figure 9 Delay Matching Waveform Definitions The 2ED2184 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the 2ED2184 (4) S06F (J) is matched to the propagation turn-on delay (tOFF). 5.4 Input logic compatibility The input pins of are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc supply voltage. With typical high threshold (VIH) of 2.1 V and typical low threshold (VIL) of 0.9 V, along with very little temperature variation as summarized in Figure 10, the input pins are conveniently driven with logic level PWM control signals derived from 3.3 V and 5 V digital power-control er devices. Wider hysteresis (typical y 0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. 2ED218x family also features tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature. The 2ED218x features floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is held in the low state. This is achieved using pull-down resistors on the input pin (IN) as Datasheet 10 of 25 V 2.10 www.infineon.com/soi 2019-09-12 Document Outline Features Product summary Product validation Description 1 Table of contents 2 Block diagram 3 Pin configuration and functionality 3.1 Pin configuration 3.2 Pin functionality 4 Electrical parameters 4.1 Absolute maximum ratings 4.2 Recommended operating conditions 4.3 Static electrical characteristics 4.4 Dynamic electrical characteristics 5 Application information and additional details 5.1 IGBT / MOSFET gate drive 5.2 Switching and timing relationships 5.3 Deadtime and matched propagation delays 5.4 Input logic compatibility 5.5 Undervoltage lockout 5.6 Shutdown Input 5.7 Bootstrap diode 5.8 Calculating the bootstrap capacitance CBS 5.9 Tolerant to negative tranisents on input pins 5.10 Negative voltage transient tolerance of VS pin 5.11 NTSOA – Negative Transient Safe Operating Area 5.12 Higher headroom for input to output signal transmission with logic operation upto -11 V 5.13 Maximum switching frequency 5.14 PCB layout tips 6 Qualification information0F 7 Related products 8 Package details 9 Part marking information 10 Additional documentation and resources 10.1 Infineon online forum resources 11 Revision history