Datasheet AD22057 (Analog Devices) - 3

AD22057 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Supply Voltage . +3.0 V to +36 V Peak Input Voltage (40 ms) . +60 V
Plastic SOIC Package
VOFS (Pin 7 to Pin 2) . +20 V
(R-8)
Reversed Supply Voltage Protection . –34 V Operating Temperature . –40°C to +125°C
–IN 1 8 +IN
Storage Temperature . –65°C to +150°C Output Short Circuit Duration . Indefinite
GND 2 AD22057 7 OFFSET TOP VIEW
Lead Temperature Range (Soldering 60 sec) . +300°C
A1 3 (Not to Scale) 6 +VS A2 4 5 OUT
*Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD22057 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
PRODUCT DESCRIPTION
offset to an optional voltage of one half of that supplied to Pin 7; The AD22057 is a single-supply difference amplifier consisting in many cases this offset would be +VS/2 by tying Pin 7 to +VS of a precision balanced attenuator, a very low drift preamplifier (Pin 6), permitting the conditioning and processing of bipolar and an output buffer amplifier (A1 and A2, respectively, in signals (see Strain Gage Interface section). Figure 2). It has been designed so that small differential sig- The output buffer A2 has a gain of ×2, setting the precalibrated, nals (VDM in Figure 3) can be accurately amplified and filtered overall gain of the AD22057, with no external components, to in the presence of large common-mode voltages (VCM) without ×20. (This gain is easily user-configurable—see Altering the the use of any other active components. Gain section for details.)
+V
The dynamic properties of the AD22057 are optimized for inter-
S OFS A1 A2
facing to transducers; in particular, current sensing shunt
AD22057
resistors. Its rejection of large, high frequency, common-mode signals makes it superior to that of many alternative approaches. This is due to the very careful design of the input attenuator and
IN+ A1 A2 OUT
the close integration of this highly balanced, high impedance
IN–
system with the preamplifier.
APPLICATIONS
The AD22057 can be used wherever a high gain, single-supply
GND
differencing amplifier is required, and where a finite input resis- tance (240 kΩ to ground, 400 kΩ between differential inputs) Figure 2. Simplified Schematic can be tolerated. In particular, the ability to handle a common- The resistive attenuator network is situated at the input to the mode input considerably larger than the supply voltage is fre- AD22057 (Pins 1 and 8), allowing the common-mode voltage at quently of value. Pins 1 and 8 to be six times greater than that which can be toler- Also, the output can run down to within 20 mV of ground, ated by the actual input to A1. As a result, the input common- provided it is not called on to sink any load current. Finally, the mode range extends to 6× (VS – 1 V). output can be offset to half of a full-scale reference voltage (with Two small filter capacitors (not shown in Figure 2) have been a tolerance of ± 2%) to allow a bipolar input signal. included at the inputs of A1 to minimize the effects of any spuri-
ALTERING THE GAIN
ous RF signals present in the signal. The gain of the preamplifier, from the attenuator input (Pins 1 Internal feedback around A1 sets the closed-loop gain of the and 8) to its output at Pin 3, is ×10 and that of the output preamplifier to ×10 from the input pins; the output of A1 is buffer, from Pin 4 to Pin 5, is ×2, thus making the overall de- connected to Pin 3 via a 100 kΩ resistor, which is trimmed to fault gain ×20. The overall gain is accurately trimmed (to within ±3% (R12 in Figure 2) to facilitate the low-pass filtering of the ±0.5%). In some cases, it may be desirable to provide for some signal of interest (see Low-Pass Filtering section). The inclusion variation in the gain; for example, in absorbing the scaling error of an additional resistive network allows the output of A1 to be of a transducer. REV. B –3–