Datasheet ADP5076 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| 页数 / 页 | 23 / 9 — Data Sheet. ADP5076. 100. A = +125°C. TA = +25°C. A = +25°C. A = –40°C. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 725 Kb |
| 文件语言 | 英语 |
Data Sheet. ADP5076. 100. A = +125°C. TA = +25°C. A = +25°C. A = –40°C. (% 60. N 50. IEN. F 40. 0.001. 0.01. 0.1. LOAD CURRENT (A). 0.5. 0.4. 0.3. (%). 0.2
该数据表的模型线
文件文字版本
Data Sheet ADP5076 100 100 T T A = +125°C A = +125°C T 90 TA = +25°C 90 A = +25°C T T A = –40°C A = –40°C 80 80 70 70 ) ) (% 60 (% 60 Y Y C C N 50 50 IE IEN IC IC F 40 F 40 EF EF 30 30 20 20 10 10 0 0
118
0.001 0.01 0.1 1
115
0.001 0.01 0.1 1
2-
LOAD CURRENT (A) LOAD CURRENT (A)
2040 20402- Figure 15. Boost Regulator Efficiency over Temperature, Figure 18. Inverting Regulator Efficiency over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5 0.5 0.4 0.4 0.3 (%) 0.3 (%) 0.2 INAL 0.2 M INAL 0.1 M 0.1 NO M NO 0 M RO O 0 F R N –0.1 F N –0.1 IO IO AT –0.2 AT –0.2 ARI RI V –0.3 A V –0.3 –0.4 V V NEG ACCURACY POS ACCURACY –0.4 V V REF ACCURACY FB1 ACCURACY VFB2 ACCURACY –0.5
5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –0.5
01 2-
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
018
V
40
IN (V)
20
VIN (V)
20402- Figure 16. Boost Regulator Line Regulation, VPOS = 15 V, Figure 19. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5 0.5 ) ) (% 1.2MHz 0.4 (% E 0.4 E 2.4MHz G 0.3 0.3 LTAG LTA O V 0.2 0.2 T VO UT P PU 0.1 T 0.1 UT U O O L 0 L 0 A INA IN M –0.1 –0.1 O OM N N –0.2 –0.2 IN IN N N –0.3 IO –0.3 IO T T A IA –0.4 1.2MHz R –0.4 ARI A V 2.4MHz V –0.5 –0.5 0 0.05 0.10 0.15 0.20 0.25
117
0 0.05 0.10 0.15 0.20
-120
LOAD CURRENT (A) LOAD CURRENT (A)
20402 20402- Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V Figure 20. Inverting Regulator Load Regulation, VIN = +5 V, VNEG = −15 V Rev. A | Page 9 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
118
0.001 0.01 0.1 1
115
0.001 0.01 0.1 1
2-
LOAD CURRENT (A) LOAD CURRENT (A)
2040 20402- Figure 15. Boost Regulator Efficiency over Temperature, Figure 18. Inverting Regulator Efficiency over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5 0.5 0.4 0.4 0.3 (%) 0.3 (%) 0.2 INAL 0.2 M INAL 0.1 M 0.1 NO M NO 0 M RO O 0 F R N –0.1 F N –0.1 IO IO AT –0.2 AT –0.2 ARI RI V –0.3 A V –0.3 –0.4 V V NEG ACCURACY POS ACCURACY –0.4 V V REF ACCURACY FB1 ACCURACY VFB2 ACCURACY –0.5
5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –0.5
01 2-
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
018
V
40
IN (V)
20
VIN (V)
20402- Figure 16. Boost Regulator Line Regulation, VPOS = 15 V, Figure 19. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5 0.5 ) ) (% 1.2MHz 0.4 (% E 0.4 E 2.4MHz G 0.3 0.3 LTAG LTA O V 0.2 0.2 T VO UT P PU 0.1 T 0.1 UT U O O L 0 L 0 A INA IN M –0.1 –0.1 O OM N N –0.2 –0.2 IN IN N N –0.3 IO –0.3 IO T T A IA –0.4 1.2MHz R –0.4 ARI A V 2.4MHz V –0.5 –0.5 0 0.05 0.10 0.15 0.20 0.25
117
0 0.05 0.10 0.15 0.20
-120
LOAD CURRENT (A) LOAD CURRENT (A)
20402 20402- Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V Figure 20. Inverting Regulator Load Regulation, VIN = +5 V, VNEG = −15 V Rev. A | Page 9 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE