Datasheet CMX655D (CML Microcircuits) - 3
| 制造商 | CML Microcircuits |
| 描述 | Ultra Low Power Voice Codec |
| 页数 / 页 | 64 / 3 — Performance Specification .. 44 |
| 修订版 | 4 |
| 文件格式/大小 | PDF / 3.3 Mb |
| 文件语言 | 英语 |
Performance Specification .. 44
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7 Performance Specification .. 44
7.1 Electrical Performance .. 44 7.1.1 Absolute Maximum Ratings .. 44 7.1.2 Operating Limits .. 44 7.1.3 Operating Characteristics .. 45 7. 2 Typical Performance Characteristics ... 52 7.2.1 THD+N vs. Level performance ... 52 7.2.2 THD+N vs. Frequency performance ... 55 7.2.3 Class D Amplifier Efficiency ... 57 7.2.4 Filter Performance Speaker Channel ... 58 7.2.5 Filter Performance Microphone Channel .. 60 7.3 Packaging... 62 7.3.1 CMX655D ... 62 Table Page Table 3 CMX655D Pin List by Number ... 6 Table 4 CMX655D Pin List by Group .. 7 Table 9 CMX655D Component Values ... 9 Table 10 CMX655D SPI Component Value ... 10 Table 11 CMX655D TWI Component Values .. 11 Table 12 External Supply Voltages ... 13 Table 13 Supply and POR Threshold Voltages ... 13 Table 15 CMX655D Slave Addresses .. 32 Table 16 Register Address Map ... 41 Table 17 SPI Timing Parameter Values .. 48 Table 18 TWI Standard Mode Timing Parameters ... 49 Table 19 TWI Fast Mode Timing Parameters ... 50 Table 20 TWI Pull-up Resistors and Bus Capacitance .. 50 Table 21 SAI Timing Parameters .. 51 Table 22 Digital Microphone Timing Parameters .. 51 Figure Page Figure 1 CMX655D Simplified Block Diagram .. 1 Figure 4 CMX655D Block Diagram ... 5 Figure 6 CMX655D Pin Arrangement ... 8 Figure 11 CMX655D Power Supply and Pin Decoupling .. 9 Figure 12 CMX655D SPI Connections... 10 Figure 13 CMX655D TWI Connections ... 11 Figure 14 CMX655D Speaker and Microphone Connections ... 12 Figure 15 Main Clock Generation .. 14 Figure 16 Integer-N PLL ... 15 Figure 17 PLL Loop Filter .. 15 Figure 18 CMX655D Digital Microphone Interface .. 18 Figure 21 Audio signal processing block diagram with gain level block highlighted .. 19 Figure 23 Audio signal processing block diagram with Noise Gate block highlighted ... 19 Figure 24 Noise Gate Response ... 20 Figure 25 Audio signal processing block diagram with Level Detect block highlighted ... 22 Figure 26 Audio signal processing block diagram with preamp block highlighted .. 23 Figure 27 Audio signal processing block diagram with the volume block highlighted ... 24 Figure 28 Audio signal processing block diagram with ALC block highlighted ... 25 Figure 29 ALC Response ... 25 Figure 30 Audio signal processing block diagram with the Digital Side Tone path and block highlighted ... 27 Figure 31 Audio signal processing block diagram with Voice Filter blocks highlighted ... 28 Figure 32 Low Pass Filter Frequency Response ... 28 Figure 33 High Pass Filter Frequency Response ... 29 Figure 34 Audio signal processing block diagram with Mic Mux and Amp Mux block highlighted ... 30 Figure 35 SPI Write Transfer .. 31 2019 CML Microsystems Plc 3 D/655/4 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655D 3 Pin List 3.1 CMX655D 4 External Components 4.1 CMX655D 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Noise Gate 5.6.2.1 Noise Gate Registers 5.6.3 Record Level Detection 5.6.3.1 Record Level Detection Registers 5.6.4 Playback Preamplifier Gain 5.6.4.1 Playback Preamplifier Gain Register 5.6.5 Playback Volume Control 5.6.5.1 Playback Volume Register 5.6.6 Automatic Level Control 5.6.6.1 ALC Registers 5.6.7 Digital Sidetone 5.6.7.1 Digital Sidetone Register 5.6.8 Voice Filters 5.6.8.1 Low Pass Filter 5.6.8.2 DC Blocking Filter 5.6.8.3 High Pass Filter 5.6.8.4 Voice Filters Registers 5.6.9 Channel Multiplexing 5.6.10 Click-and-Pop Reduction 5.6.10.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 Configuration 6.1.3 Enable Audio Channels 6.1.4 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D End of Document cmlmicro.com CMX655D - Ultra-low Power Voice Codec - CML Micro
7 Performance Specification .. 44
7.1 Electrical Performance .. 44 7.1.1 Absolute Maximum Ratings .. 44 7.1.2 Operating Limits .. 44 7.1.3 Operating Characteristics .. 45 7. 2 Typical Performance Characteristics ... 52 7.2.1 THD+N vs. Level performance ... 52 7.2.2 THD+N vs. Frequency performance ... 55 7.2.3 Class D Amplifier Efficiency ... 57 7.2.4 Filter Performance Speaker Channel ... 58 7.2.5 Filter Performance Microphone Channel .. 60 7.3 Packaging... 62 7.3.1 CMX655D ... 62 Table Page Table 3 CMX655D Pin List by Number ... 6 Table 4 CMX655D Pin List by Group .. 7 Table 9 CMX655D Component Values ... 9 Table 10 CMX655D SPI Component Value ... 10 Table 11 CMX655D TWI Component Values .. 11 Table 12 External Supply Voltages ... 13 Table 13 Supply and POR Threshold Voltages ... 13 Table 15 CMX655D Slave Addresses .. 32 Table 16 Register Address Map ... 41 Table 17 SPI Timing Parameter Values .. 48 Table 18 TWI Standard Mode Timing Parameters ... 49 Table 19 TWI Fast Mode Timing Parameters ... 50 Table 20 TWI Pull-up Resistors and Bus Capacitance .. 50 Table 21 SAI Timing Parameters .. 51 Table 22 Digital Microphone Timing Parameters .. 51 Figure Page Figure 1 CMX655D Simplified Block Diagram .. 1 Figure 4 CMX655D Block Diagram ... 5 Figure 6 CMX655D Pin Arrangement ... 8 Figure 11 CMX655D Power Supply and Pin Decoupling .. 9 Figure 12 CMX655D SPI Connections... 10 Figure 13 CMX655D TWI Connections ... 11 Figure 14 CMX655D Speaker and Microphone Connections ... 12 Figure 15 Main Clock Generation .. 14 Figure 16 Integer-N PLL ... 15 Figure 17 PLL Loop Filter .. 15 Figure 18 CMX655D Digital Microphone Interface .. 18 Figure 21 Audio signal processing block diagram with gain level block highlighted .. 19 Figure 23 Audio signal processing block diagram with Noise Gate block highlighted ... 19 Figure 24 Noise Gate Response ... 20 Figure 25 Audio signal processing block diagram with Level Detect block highlighted ... 22 Figure 26 Audio signal processing block diagram with preamp block highlighted .. 23 Figure 27 Audio signal processing block diagram with the volume block highlighted ... 24 Figure 28 Audio signal processing block diagram with ALC block highlighted ... 25 Figure 29 ALC Response ... 25 Figure 30 Audio signal processing block diagram with the Digital Side Tone path and block highlighted ... 27 Figure 31 Audio signal processing block diagram with Voice Filter blocks highlighted ... 28 Figure 32 Low Pass Filter Frequency Response ... 28 Figure 33 High Pass Filter Frequency Response ... 29 Figure 34 Audio signal processing block diagram with Mic Mux and Amp Mux block highlighted ... 30 Figure 35 SPI Write Transfer .. 31 2019 CML Microsystems Plc 3 D/655/4 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655D 3 Pin List 3.1 CMX655D 4 External Components 4.1 CMX655D 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Noise Gate 5.6.2.1 Noise Gate Registers 5.6.3 Record Level Detection 5.6.3.1 Record Level Detection Registers 5.6.4 Playback Preamplifier Gain 5.6.4.1 Playback Preamplifier Gain Register 5.6.5 Playback Volume Control 5.6.5.1 Playback Volume Register 5.6.6 Automatic Level Control 5.6.6.1 ALC Registers 5.6.7 Digital Sidetone 5.6.7.1 Digital Sidetone Register 5.6.8 Voice Filters 5.6.8.1 Low Pass Filter 5.6.8.2 DC Blocking Filter 5.6.8.3 High Pass Filter 5.6.8.4 Voice Filters Registers 5.6.9 Channel Multiplexing 5.6.10 Click-and-Pop Reduction 5.6.10.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 Configuration 6.1.3 Enable Audio Channels 6.1.4 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D End of Document cmlmicro.com CMX655D - Ultra-low Power Voice Codec - CML Micro