Data Brief SZ1105 (Silanna) - 3

PRODUCT BRIEF SZ1105 Typical Application Circuit
VBULK Primary Secondary VOUT COUT Secondary FET R * DAMP C * BST * Primary FET ZBST * V5OUT CC SR1 CBULK * * DCL D * R BST GATE RSENSE Sync Rec DGATE BOOT_CL (4) SW (3) ISNS (11) GATE (8) Startup Regulator Active Clamp Regulator1 Auxiliary FET V10 (7) D * AUX CLAMP (1) C Disconnect FET V V10 CA BUS 2 5V RC1 LDO Active Main V5OUT (13) Clamp Switch LS Driver ISENSE Driver C R V5OUT sns CLMP_S (16) COMPS R U PU 1 AC NTC R CC2 COMPS C2 OptiM COMP TEMP (9) USB-PD Bandgap R 0 t OptiMode T2 - R1 C1 R USB-PD C B1 2 Digital RA1 VAUX_S (14) VBULK_S (15) VBULK Clock COMPS Gen QR COMP CA2 R VOUT R A2 B2 CB2 PulseLink A V5OUT D Encoder/Decoder C RFB RS1 O1 FB (12) RS2 DGND (10) GND (6)
Figure 4. Typical Application Circuit of an USB-PD Active Clamp Flyback Converter using SZ1105
Notes: * Critical components are identified with red dotted circles. Careful considerations are required when selecting these components for reliable operation of the device. 1. The discrete regulator is required for applications as the output voltage varies over a wide range in USB-PD applications (5-20 V). 2 Removing RC1 and RC2 resistors and connecting CLMP_S pin to V5OUT pin results in conducted EMI suppression above 2 MHz with a minimal efficiency penalty (~0.1%). Silanna Semiconductor Proprietary and Confidential Page 3 For more information: www.SilannaSemi.com Document 10854 Ver. 3.0