Datasheet HT32F59041 (Holtek) - 8

Enhanced 24-bit A/D Arm® Cortex®-M0+ MCU HT32F59041
Reset Control Unit – RSTCU
▆ Supply supervisor: ● Power on Reset / Power down Reset – POR / PDR ● Brown-out Detector – BOD ● Programmable Low Voltage Detector – LVD The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
2 Features
A system reset resets the processor core and peripheral IP components with the exception of the SW-DP controller. The resets can be triggered by external signals, internal events and the reset generators.
Clock Control Unit – CKCU
▆ External 4 to 20 MHz crystal oscillator ▆ External 32.768 kHz crystal oscillator ▆ Internal 20 MHz RC oscillator trimmed to ±2 % accuracy at 25 °C operating temperature ▆ Internal 32 kHz RC oscillator ▆ Independent clock divider and gating bits for peripheral clock sources The Clock Control Unit, CKCU, provides a range of oscillator and clock functions. These include a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), an HSE clock monitor, clock pre-scalers, clock multiplexers, APB clock divider and gating circuitry. The AHB, APB and Cortex®-M0+ clocks are derived from the system clock (CK_SYS) which can come from the HSI, HSE, LSI or LSE. The Watchdog Timer and Real Time Clock (RTC) use either the LSI or LSE as their clock source.
Power Management Control Unit – PWRCU
▆ Single VDD power supply: 2.5 V to 5.5 V ▆ Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply ▆ Two power domains: VDD and 1.5 V ▆ Three power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 Power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, in the device provides many types of power saving modes such as Sleep, Deep-Sleep1 and Deep-Sleep2 mode. These operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conflicting demands of CPU operating time, speed and power consumption. Rev. 1.00 8 of 59 January 17, 2020 Document Outline 1 General Description 2 Features Core On-chip Memory Flash Memory Controller – FMC Reset Control Unit – RSTCU Clock Control Unit – CKCU Power Management Control Unit – PWRCU Real Time Clock – RTC External Interrupt / Event Controller – EXTI Hardware Divider – DIV 12-Bit Analog to Digital Converter – ADC 24-Bit Delta Sigma Analog to Digital Converter – ΔΣ ADC I/O Ports – GPIO Basic Function Timer – BFTM Motor Control Timer – MCTM PWM Generation and Capture Timer – GPTM Pulse Width Modulation – PWM Watchdog Timer – WDT Inter-integrated Circuit – I2C Serial Peripheral Interface – SPI Universal Synchronous Asynchronous Receiver Transmitter – USART Universal Asynchronous Receiver Transmitter – UART Cyclic Redundancy Check – CRC Debug Support Package and Operation Temperature 3 Overview Device Information Block Diagram Memory Map Clock Structure 4 24-Bit Delta Sigma A/D Converter – ΔΣ ADC 24-Bit A/D Converter Internal Registers Internal Power Supply Reference Voltages Power and Reference Control Oscillator Input Signal Gain Control Amplifier – PGA 24-Bit Analog to Digital Converter Operation External Interface Communication 5 Pin Assignment 6 Electrical Characteristics Absolute Maximum Ratings Recommended DC Operating Conditions On-Chip LDO Voltage Regulator Characteristics Power Consumption Reset and Supply Monitor Characteristics External Clock Characteristics Internal Clock Characteristics Memory Characteristics I/O Port Characteristics 12-Bit ADC Characteristics 24-Bit ADC Characteristics Effective Number of Bits (ENOB) MCTM/GPTM/PWM Characteristics I2C Characteristics SPI Characteristics 7 Package Information 48-pin LQFP (7mm × 7mm) Outline Dimensions