Datasheet STSPIN32F0601, STSPIN32F0602 (STMicroelectronics) - 10

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Electrical characteristics STSPIN32F0601, STSPIN32F0602 4 Electrical characteristics
(VCC=15 V; VDD=3.3 V; PGND = SGND; TJ = +25 °C, unless otherwise specified.)
Table 7. Electrical characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit Power supply and standby mode
VCC undervoltage VCC = 7 V; IQCCU quiescent supply 430 744 μA current EN = 5 V; CIN = SGND VCC quiescent EN = 5 V; CIN = SGND IQCC 950 1450 μA supply current LVG & HVG: OFF VCC UVLO turn-on VCCthON 8 8.5 9 V threshold VCC UVLO turn-off VCCthOFF 7.5 8 8.5 V threshold VCC UVLO VCChys 0.4 0.5 0.6 V threshold hysteresis VDD = 3.6 V VDD current consumption HSE bypass, PLL off 0.8 fHCLK = 1 MHz I (1) (Supply current in DD mA Run mode, code VDD = 3.6 V executing from HSI clock, PLL on 18.9 Flash memory) fHCLK = 48 MHz VDD = 3.6 V HSE bypass, PLL off 2.0 fHCLK = 1 MHz I (1) VDDA current DDA μA consumption VDD = 3.6 V HSI clock, PLL on 220 fHCLK = 48 MHz VDD Power on reset VPOR Rising edge 1.84(2) 1.92 2.00 V threshold VDD Power down VPDR Falling edge 1.80 1.88 1.96(2) V reset threshold VDD PDR VPDRhyst 40 mV hysteresis
High-side floating section supply(3)
VBO under-voltage VCC = VBO = 6.5 V; IQBOU quiescent supply 25 62 μA current EN = 5 V; CIN = SGND VBO = 15 V V I BO quiescent QBO EN = 5 V; CIN = SGND 84 150 μA supply current LVG OFF; HVG = ON 10/29 DS12981 Rev 3 Document Outline 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F060x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history