Datasheet BridgeSwitch Family (Power Integrations) - 7

BridgeSwitch Power-Up Sequence with Self-Supply
BridgeSwitch devices have internal self-supply supporting commuta- tion PWM frequencies up to 20 kHz. To ensure a sufficient supply voltage levels across the BYPASS LOW-SIDE pin capacitor and the INL BYPASS HIGH-SIDE pin capacitor at inverter start-up, the system micro-control er (MCU) should fol ow the recommended power-up sequence depicted in Figure 9. Table 2 lists activities occurring during the recommended power-up /INH sequence. (ON) (ON) The BYPASS LOW-SIDE pin capacitor C , the BPL pin charge current BPL LS GATE I , and the BYPASS LOW-SIDE pin voltage V determine the CH1(LS) BPL DRIVE (OFF) (OFF) charging time t starting at time point t1: BPLC t BPL × B PL HS GATE (ON) (ON) BPLC = t – t C V = 2 1 ICH1(LS) DRIVE (OFF) (OFF) The system MCU manages the power-up sequence by controlling the a) b) time point t2 and duration t for turning on and off the low-side power INLS FREDFET. The MCU may pull the CONTROL INPUT LOW-SIDE pin high PI-8298-032817 any time after the full DC bus voltage is available (time point t ). 1 Figure 10. Simultaneous Conduction Lockout a) Not Active b) Active. However, the device enables power MOSEFT switching only after the BYPASS LOW-SIDE pin voltages reaches V (typical y 14.5 V) and the BPL device setup completes. operation. The high-side power FREDFET latches on or off with the The high-side control er reports internal y its status to the low-side edge of the active low /INH signal. The INL input has an internal control er at time point t3 after the BYPASS HIGH-SIDE pin voltage weak pul -down and the /INH input has an internal weak pull-up. reaches V (typical y 14.5 V) with respect to the HALF-BRIDGE This prevents accidental power FREDFET turn-on in case one or both BPH CONNECTION pin. This is fol owed by a device status update to the control inputs are floating. system MCU through the STATUS COMMUNICATION pin. BridgeSwitch integrates simultaneous conduction lockout protection. A minimum low-side FREDFET on-time t is required for charging A latch inhibits turning on the low-side power FREDFET Gate drive INLS the BYPASS HIGH-SIDE pin capacitor, device setup, and status update circuitry until the rising edge of the high-side control signal /INH has communication through the FAULT pin. It is control ed by the system occurred (see Figure 10). The latch also inhibits turning on the MCU and depends on the selected capacitance CBPH: high-side power FREDFET Gate drive circuitry until the falling edge of the low-side control signal INL has occurred. t INLS = t4 – t CBPH × VBPH 2 ≥ I +1 ms The inverse logic polarity of INL and /INH control inputs al ows CH1 (HS ) The system MCU should proceed with the power-up sequence optional y tying both together for controlling both power FREDFETs with described above, if a latching thermal shutdown had occurred and it a single PWM signal. To prevent possible FREDFET cross conduction, decides to restart the inverter by first sending a FAULT latch reset the integrated Gate drive logic applies adaptive dead times as shown in command (see Table 7 for details). Figure 11. The falling edge of the low-side power FREDFET control input INL triggers the t timer (Dead Time low-side power FREDFET DLH
Gate Drive Control Inputs
off to high-side power FREDFET on). The integrated Gate control logic The low-side and high-side power FREDFETs are control ed through enables turning on the high-side FREDFET Gate drive only after t DLH INL and /INH logic inputs. Both inputs are compatible with 3.3 V and expires. The rising edge of the high-side power FREDFET control input 5 V CMOS logic levels. The low-side power FREDFET latches on or off /INH triggers the t timer (Dead Time high-side power FREDFET off to DHL with the edge of the active high INL signal during steady-state low-side power FREDFET on). The integrated Gate control logic enables turning on the low-side FREDFET Gate drive only after t expires. DHL
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Rev. I 01/20 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description BridgeSwitch Functional Description Application Example PCB Design Guidelines Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Characteristics inSOP-24C Package Drawing Package Marking Part Ordering and MSL Table ESD and Latch-Up Table Part Ordering Information