Datasheet ADAU1788 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Two ADCs, One DAC, Low Power Codec with Audio DSPs |
| 页数 / 页 | 226 / 1 — Two ADCs, One DAC,. Low Power Codec with Audio DSPs. Data Sheet. … |
| 文件格式/大小 | PDF / 3.0 Mb |
| 文件语言 | 英语 |
Two ADCs, One DAC,. Low Power Codec with Audio DSPs. Data Sheet. ADAU1788. FEATURES. GENERAL DESCRIPTION
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Two ADCs, One DAC, Low Power Codec with Audio DSPs Data Sheet ADAU1788 FEATURES GENERAL DESCRIPTION Programmable FastDSP audio processing engine
The ADAU1788 is a codec with two inputs and one output that
Up to 768 kHz sample rate
incorporates two digital signal processors (DSPs). The path
Biquad filters, limiters, volume controls, mixing
from the analog input to the DSP core to the analog output is
28-bit SigmaDSP audio processing core
optimized for low latency and is ideal for noise cancel ing
Visually programmable using SigmaStudio
headsets. With the addition of just a few passive components,
Up to 50 MIPS performance
the ADAU1788 provides a noise cancel ing headphone solution.
Low latency, 24-bit ADCs and DAC 96 dB SNR (signal through PGA and ADC with
Note that throughout this data sheet, multifunction pins, such
A-weighted filter)
as BCLK_0/MP1, are referred to either by the entire pin name
105 dB combined SNR (signal through DAC and headphone
or by a single function of the pin, for example, BCLK_0, when
with A-weighted filter)
only that function is relevant.
Serial port fSYNC frequency from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out 2 single-ended analog inputs, configurable as microphone or line inputs 4 digital microphone inputs 1 analog differential audio output, configurable as either line output or headphone driver PLL supporting any input clock rate from 30 kHz to 27 MHz Full-duplex, 4-channel ASRCs 16-channel serial audio port supporting I2S, left justified, or up to TDM16 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.9 V typical Low power (8.030 mW for typical power consumption) I2C and SPI control interfaces Flexible GPIO 42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras Musical instrument effect processors Multimedia speaker systems Smartphones Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1788 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Output Pop and Click Suppression DAC DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE SIGNAL PROCESSING DETAILS Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC BIAS CURRENT CONTROL DAC BIAS CURRENT CONTROL DAC LOW POWER MODES PLL BYPASS SigmaDSP CLOCK SPEED CONTROL ASYNCHRONOUS SAMPLE RATE CONVERTERS LOW POWER MODES CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/ Subaddress Data Bytes MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORT APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ANALOG DEVICES VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, AND HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLOCK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (MSBs) REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs) REGISTER PLL FRACTIONAL NUMERATOR VALUE (MSBs) REGISTER PLL FRACTIONAL NUMERATOR VALUE (LSBs) REGISTER PLL FRACTIONAL DENOMINATOR (MSBs) REGISTER PLL FRACTIONAL DENOMINATOR (LSBs) REGISTER PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HIGH-PASS FILTER CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, AND SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, AND SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DMIC CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DMIC VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LUNK, HIGH-PASS FILTER, AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0/CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2/CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4/CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6/CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0/PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2/PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4/PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6/PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8/PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PINS 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER MP3 PIN CONTROLS REGISTER MP4 PIN CONTROLS REGISTER MP5 PIN CONTROLS REGISTER MP6 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT) REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT) REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
The ADAU1788 is a codec with two inputs and one output that
Up to 768 kHz sample rate
incorporates two digital signal processors (DSPs). The path
Biquad filters, limiters, volume controls, mixing
from the analog input to the DSP core to the analog output is
28-bit SigmaDSP audio processing core
optimized for low latency and is ideal for noise cancel ing
Visually programmable using SigmaStudio
headsets. With the addition of just a few passive components,
Up to 50 MIPS performance
the ADAU1788 provides a noise cancel ing headphone solution.
Low latency, 24-bit ADCs and DAC 96 dB SNR (signal through PGA and ADC with
Note that throughout this data sheet, multifunction pins, such
A-weighted filter)
as BCLK_0/MP1, are referred to either by the entire pin name
105 dB combined SNR (signal through DAC and headphone
or by a single function of the pin, for example, BCLK_0, when
with A-weighted filter)
only that function is relevant.
Serial port fSYNC frequency from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out 2 single-ended analog inputs, configurable as microphone or line inputs 4 digital microphone inputs 1 analog differential audio output, configurable as either line output or headphone driver PLL supporting any input clock rate from 30 kHz to 27 MHz Full-duplex, 4-channel ASRCs 16-channel serial audio port supporting I2S, left justified, or up to TDM16 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.9 V typical Low power (8.030 mW for typical power consumption) I2C and SPI control interfaces Flexible GPIO 42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras Musical instrument effect processors Multimedia speaker systems Smartphones Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1788 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Output Pop and Click Suppression DAC DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE SIGNAL PROCESSING DETAILS Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC BIAS CURRENT CONTROL DAC BIAS CURRENT CONTROL DAC LOW POWER MODES PLL BYPASS SigmaDSP CLOCK SPEED CONTROL ASYNCHRONOUS SAMPLE RATE CONVERTERS LOW POWER MODES CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/ Subaddress Data Bytes MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORT APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ANALOG DEVICES VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, AND HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLOCK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (MSBs) REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs) REGISTER PLL FRACTIONAL NUMERATOR VALUE (MSBs) REGISTER PLL FRACTIONAL NUMERATOR VALUE (LSBs) REGISTER PLL FRACTIONAL DENOMINATOR (MSBs) REGISTER PLL FRACTIONAL DENOMINATOR (LSBs) REGISTER PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HIGH-PASS FILTER CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, AND SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, AND SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DMIC CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DMIC VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LUNK, HIGH-PASS FILTER, AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0/CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2/CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4/CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6/CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0/PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2/PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4/PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6/PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8/PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PINS 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER MP3 PIN CONTROLS REGISTER MP4 PIN CONTROLS REGISTER MP5 PIN CONTROLS REGISTER MP6 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT) REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT) REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE