Datasheet ADAU1787 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Four ADC, Two DAC, Low Power Codec with Audio DSPs |
| 页数 / 页 | 280 / 7 — Data Sheet. ADAU1787. SPECIFICATIONS. ANALOG PERFORMANCE SPECIFICATIONS. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.9 Mb |
| 文件语言 | 英语 |
Data Sheet. ADAU1787. SPECIFICATIONS. ANALOG PERFORMANCE SPECIFICATIONS. Table 1. Parameter Test. Conditions/Comments. Min. Typ. Max
该数据表的模型线
文件文字版本
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Data Sheet ADAU1787 SPECIFICATIONS
Master clock input = 24.576 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature (TA) = 25°C, and line output load = 10 kΩ, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V and DVDD = 0.9 V, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution All ADCs 24 Bits Digital Gain Step 0.375 dB Digital Gain Range −71 +24 dB INPUT RESISTANCE Single-Ended Line Input 14.3 kΩ Programmable Gain Amplifier (PGA) 0 dB gain 20.26 kΩ Inputs 32 dB gain 0.97 kΩ SINGLE-ENDED LINE INPUT PGAx_EN = 0, PGAx_BOOST = 0, PGAx_SLEW_DIS = 1 Full-Scale Input Voltage 0 dBFS 0.49 V rms 0 dBFS 1.38 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) 97 dB With Flat 20 Hz to 20 kHz Filter 94 dB Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) 98 dB With Flat 20 Hz to 20 kHz Filter 96 dB Interchannel Gain Mismatch 40 mdB Total Harmonic Distortion + Noise 20 Hz to 20 kHz, −1 dB full-scale output (THD + N) Level −90 dBFS Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CM capacitor = 10 μF 100 dB Power Supply Rejection Ratio (PSRR) CM capacitor = 10 μF 100 mV p-p at 1 kHz 60 dB 100 mV p-p at 10 kHz 40 dB SINGLE-ENDED PGA INPUT PGAx_EN = 1, PGA_x_BOOST = 0 Full-Scale Input Voltage 0.49 V rms 0 dBFS 1.38 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) 96 dB With Flat 20 Hz to 20 kHz Filter 94 dB THD + N Level 20 Hz to 20 kHz, −1 dBFS output −88 dBFS SNR2 With A-Weighted Filter (RMS) 96 dB With Flat 20 Hz to 20 kHz Filter 94 dB PGA Gain Variation Standard deviation With 0 dB Setting 0.05 dB With 35.25 dB Setting 0.15 dB PGA Boost PGA_x_BOOST 10 dB Interchannel Gain Mismatch 0.005 dB Rev. A | Page 7 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADAU1787 SPECIFICATIONS
Master clock input = 24.576 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature (TA) = 25°C, and line output load = 10 kΩ, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V and DVDD = 0.9 V, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution All ADCs 24 Bits Digital Gain Step 0.375 dB Digital Gain Range −71 +24 dB INPUT RESISTANCE Single-Ended Line Input 14.3 kΩ Programmable Gain Amplifier (PGA) 0 dB gain 20.26 kΩ Inputs 32 dB gain 0.97 kΩ SINGLE-ENDED LINE INPUT PGAx_EN = 0, PGAx_BOOST = 0, PGAx_SLEW_DIS = 1 Full-Scale Input Voltage 0 dBFS 0.49 V rms 0 dBFS 1.38 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) 97 dB With Flat 20 Hz to 20 kHz Filter 94 dB Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) 98 dB With Flat 20 Hz to 20 kHz Filter 96 dB Interchannel Gain Mismatch 40 mdB Total Harmonic Distortion + Noise 20 Hz to 20 kHz, −1 dB full-scale output (THD + N) Level −90 dBFS Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CM capacitor = 10 μF 100 dB Power Supply Rejection Ratio (PSRR) CM capacitor = 10 μF 100 mV p-p at 1 kHz 60 dB 100 mV p-p at 10 kHz 40 dB SINGLE-ENDED PGA INPUT PGAx_EN = 1, PGA_x_BOOST = 0 Full-Scale Input Voltage 0.49 V rms 0 dBFS 1.38 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) 96 dB With Flat 20 Hz to 20 kHz Filter 94 dB THD + N Level 20 Hz to 20 kHz, −1 dBFS output −88 dBFS SNR2 With A-Weighted Filter (RMS) 96 dB With Flat 20 Hz to 20 kHz Filter 94 dB PGA Gain Variation Standard deviation With 0 dB Setting 0.05 dB With 35.25 dB Setting 0.15 dB PGA Boost PGA_x_BOOST 10 dB Interchannel Gain Mismatch 0.005 dB Rev. A | Page 7 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE