Datasheet ADAU1772 (Analog Devices) - 10

ADAU1772 Data Sheet DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing Limit Parameter TMIN TMAX Unit Description
MASTER CLOCK tMP 37 125 ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL tMCLK 77 82 ns Internal MCLK period; direct MCLK and PLL output divided by 2 SERIAL PORT tBL 40 ns BCLK low pulse width (master and slave modes) tBH 40 ns BCLK high pulse width (master and slave modes) tLS 10 ns LRCLK setup; time to BCLK rising (slave mode) tLH 10 ns LRCLK hold; time from BCLK rising (slave mode) tSS 5 ns DAC_SDATA setup; time to BCLK rising (master and slave modes) tSH 5 ns DAC_SDATA hold; time from BCLK rising (master and slave modes) tTS 10 ns BCLK falling to LRCLK timing skew (master mode) tSOD 0 34 ns ADC_SDATAx delay; time from BCLK fal ing (master and slave modes) tSOTD 30 ns BCLK fal ing to ADC_SDATAx driven in TDM tristate mode tSOTX 30 ns BCLK fal ing to ADC_SDATAx tristated in TDM tristate mode SPI PORT fSCLK 6.25 MHz SCLK frequency tCCPL 80 ns SCLK pulse width low tCCPH 80 ns SCLK pulse width high tCLS 5 ns SS setup; time to SCLK rising tCLH 100 ns SS hold; time from SCLK rising tCLPH 80 ns SS pulse width high tCDS 10 ns MOSI setup; time to SCLK rising tCDH 10 ns MOSI hold; time from SCLK rising tCOD 101 ns MISO delay; time from SCLK falling I2C PORT fSCL 400 kHz SCL frequency tSCLH 0.6 µs SCL high tSCLL 1.3 µs SCL low tSCS 0.6 µs SCL rise setup time (to SDA falling), relevant for repeated start condition tSCR 250 ns SCL and SDA rise time, CLOAD = 400 pF tSCH 0.6 µs SCL fall hold time (from SDA falling), relevant for start condition tDS 100 ns SDA setup time (to SCL rising) tSCF 250 ns SCL fall time; CLOAD = 400 pF tSDF 250 ns SDA fall time; CLOAD = 400 pF tBFT 0.6 µs SCL rise setup time (to SDA rising), relevant for stop condition I2C EEPROM SELF-BOOT tSCHE 26 × tMP – 70 ns SCL fall hold time (from SDA falling), relevant for start condition; tMP is the input clock on the MCLKIN pin tSCSE 38 × tMP – 70 ns SCL rise setup time (to SDA falling), relevant for repeated start condition tBFTE 70 × tMP – 70 ns SCL rise setup time (to SDA rising), relevant for stop condition tDSE 6 × tMP – 70 ns Delay from SCL falling to SDA changing tBHTE 32 × tMP ns SDA rising in self-boot stop condition to SDA falling edge for external master start condition MULTIPURPOSE AND POWER- DOWN PINS tGIL 1.5 × 1/fS µs MPx input latency; time until high or low value is read by core tRLPW 20 ns PD low pulse width Rev. C | Page 10 of 116 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Crystal Amplifier Specifications Digital Input/Output Specifications Power Supply Specifications Typical Power Consumption Digital Filters Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation System Clocking and Power-Up Clock Initialization PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode Clock Output Power Sequencing Power-Down Considerations Signal Routing Input Signal Paths Analog Inputs Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias Digital Microphone Input Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Output Signal Paths Analog Outputs Headphone Output Headphone Output Power-Up Sequencing Ground-Centered Headphone Configuration Pop-and-Click Suppression Line Outputs Digital-to-Analog Converters DAC Full-Scale Level Digital DAC Volume Control PDM Output Asynchronous Sample Rate Converters Signal Levels Signal Processing Instructions Data Memory Parameters Control Port Burst Mode Communication I2C Port Addressing I2C Read and Write Operations SPI Port Read/Write Subaddress Data Bytes Self-Boot EEPROM Size CRC Delay Boot Time Multipurpose Pins Push-Button Volume Controls Limiter Compression Enable Parameter Bank Switching Mute DSP Bypass Mode Serial Data Input/Output Ports Tristating Unused Channels Applications Information Power Supply Bypass Capacitors Layout Grounding Exposed Pad PCB Design Register Summary Register Details Clock Control Register PLL Denominator MSB Register PLL Denominator LSB Register PLL Numerator MSB Register PLL Numerator LSB Register PLL Integer Setting Register PLL Lock Flag Register CLKOUT Setting Selection Register Regulator Control Register Core Control Register Filter Engine and Limiter Control Register DB Value Register 0 Read DB Value Register 1 Read DB Value Register 2 Read Core Channel 0/Core Channel 1 Input Select Register Core Channel 2/Core Channel 3 Input Select Register DAC Input Select Register PDM Modulator Input Select Register Serial Data Output 0/Serial Data Output 1 Input Select Register Serial Data Output 2/Serial Data Output 3 Input Select Register Serial Data Output 4/Serial Data Output 5 Input Select Register Serial Data Output 6/Serial Data Output 7 Input Select Register ADC_SDATA0/ADC_SDATA1 Channel Select Register Output ASRC0/Output ASRC1 Source Register Output ASRC2/Output ASRC3 Source Register Input ASRC Channel Select Register ADC0/ADC1 Control 0 Register ADC2/ADC3 Control 0 Register ADC0/ADC1 Control 1 Register ADC2/ADC3 Control 1 Register ADC0 Volume Control Register ADC1 Volume Control Register ADC2 Volume Control Register ADC3 Volume Control Register PGA Control 0 Register PGA Control 1 Register PGA Control 2 Register PGA Control 3 Register PGA Slew Control Register PGA 10 dB Gain Boost Register Input and Output Capacitor Charging Register DSP Bypass Path Register DSP Bypass Gain for PGA0 Register DSP Bypass Gain for PGA1 Register MIC_BIAS0_1 Control Register DAC Control Register DAC0 Volume Control Register DAC1 Volume Control Register Headphone Output Mutes Register Serial Port Control 0 Register Serial Port Control 1 Register TDM Output Channel Disable Register PDM Enable Register PDM Pattern Setting Register MP0 Function Setting Register MP1 Function Setting Register MP2 Function Setting Register MP3 Function Setting Register MP4 Function Setting Register MP5 Function Setting Register MP6 Function Setting Register Push-Button Volume Settings Register Push-Button Volume Control Assignment Register Debounce Modes Register Headphone Line Output Select Register Decimator Power Control Register ASRC Interpolator and DAC Modulator Power Control Register Analog Bias Control 0 Register Analog Bias Control 1 Register Digital Pin Pull-Up Control 0 Register Digital Pin Pull-Up Control 1 Register Digital Pin Pull-Down Control 0 Register Digital Pin Pull-Down Control 1 Register Digital Pin Drive Strength Control 0 Register Digital Pin Drive Strength Control 1 Register Outline Dimensions Ordering Guide