Datasheet ADAU1361 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| 页数 / 页 | 80 / 1 — Stereo, Low Power, 96 kHz, 24-Bit. Audio Codec with Integrated PLL. Data … |
| 修订版 | D |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Stereo, Low Power, 96 kHz, 24-Bit. Audio Codec with Integrated PLL. Data Sheet. ADAU1361. FEATURES. GENERAL DESCRIPTION
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Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL Data Sheet ADAU1361 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC: >98 dB SNR
The ADAU1361 is a low power, stereo audio codec that supports
Sampling rates from 8 kHz to 96 kHz
stereo 48 kHz record and playback at 14 mW from a 1.8 V analog
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
supply. The stereo audio ADCs and DACs support sample rates
6 analog input pins, configurable for single-ended or
from 8 kHz to 96 kHz as well as a digital volume control. The
differential inputs
ADAU1361 is ideal for battery-powered audio and telephony
Flexible analog input/output mixers
applications.
Stereo digital microphone input
The record path includes an integrated microphone bias circuit
Analog outputs: 2 differential stereo, 2 single-ended stereo,
and six inputs. The inputs can be mixed and muxed before the
1 mono headphone output driver
ADC, or they can be configured to bypass the ADC. The
PLL supporting input clocks from 8 MHz to 27 MHz
ADAU1361 includes a stereo digital microphone input.
Analog automatic level control (ALC) Microphone bias reference voltage
The ADAU1361 includes five high power output drivers (two
Analog and digital I/O: 1.8 V to 3.65 V
differential and three single-ended), supporting stereo head-
I2C and SPI control interfaces
phones, an earpiece, or other output transducer. AC-coupled
Digital audio serial data I/O: stereo and time-division
or capless configurations are supported. Individual fine level
multiplexing (TDM) modes
controls are supported on all analog outputs. The output mixer
Software-controllable clickless mute
stage allows for flexible routing of audio.
Software power-down
The serial control bus supports the I2C and SPI protocols. The
32-lead, 5 mm × 5 mm LFCSP
serial audio bus is programmable for I2S, left-/right-justified,
−40°C to +85°C operating temperature range
and TDM modes. A programmable PLL supports flexible clock
APPLICATIONS
generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHz.
Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products FUNCTIONAL BLOCK DIAGRAM UT D D ND DDO DD DD ND ND CM IOV DG DV AV AV AG AG HP JACK REGULATOR JACKDET/MICIN ADAU1361 DETECTION LAUX LOUTP LINP LOUTN ADC DAC LHP LINN INPUT MIXERS ADC DAC OUTPUT MONOOUT DIGITAL DIGITAL MIXERS RINP ALC FILTERS FILTERS RHP ADC DAC RINN ROUTP RAUX ROUTN MICROPHONE MICBIAS PLL SERIAL DATA I2C/SPI BIAS INPUT/OUTPUT PORTS CONTROL PORT MCLK ADC_SDATA K K DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
001
CLATCH CDATA CCLK COUT BCL RCL L
07679- Figure 1.
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/ Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) Outline Dimensions Ordering Guide
The ADAU1361 is a low power, stereo audio codec that supports
Sampling rates from 8 kHz to 96 kHz
stereo 48 kHz record and playback at 14 mW from a 1.8 V analog
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
supply. The stereo audio ADCs and DACs support sample rates
6 analog input pins, configurable for single-ended or
from 8 kHz to 96 kHz as well as a digital volume control. The
differential inputs
ADAU1361 is ideal for battery-powered audio and telephony
Flexible analog input/output mixers
applications.
Stereo digital microphone input
The record path includes an integrated microphone bias circuit
Analog outputs: 2 differential stereo, 2 single-ended stereo,
and six inputs. The inputs can be mixed and muxed before the
1 mono headphone output driver
ADC, or they can be configured to bypass the ADC. The
PLL supporting input clocks from 8 MHz to 27 MHz
ADAU1361 includes a stereo digital microphone input.
Analog automatic level control (ALC) Microphone bias reference voltage
The ADAU1361 includes five high power output drivers (two
Analog and digital I/O: 1.8 V to 3.65 V
differential and three single-ended), supporting stereo head-
I2C and SPI control interfaces
phones, an earpiece, or other output transducer. AC-coupled
Digital audio serial data I/O: stereo and time-division
or capless configurations are supported. Individual fine level
multiplexing (TDM) modes
controls are supported on all analog outputs. The output mixer
Software-controllable clickless mute
stage allows for flexible routing of audio.
Software power-down
The serial control bus supports the I2C and SPI protocols. The
32-lead, 5 mm × 5 mm LFCSP
serial audio bus is programmable for I2S, left-/right-justified,
−40°C to +85°C operating temperature range
and TDM modes. A programmable PLL supports flexible clock
APPLICATIONS
generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHz.
Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products FUNCTIONAL BLOCK DIAGRAM UT D D ND DDO DD DD ND ND CM IOV DG DV AV AV AG AG HP JACK REGULATOR JACKDET/MICIN ADAU1361 DETECTION LAUX LOUTP LINP LOUTN ADC DAC LHP LINN INPUT MIXERS ADC DAC OUTPUT MONOOUT DIGITAL DIGITAL MIXERS RINP ALC FILTERS FILTERS RHP ADC DAC RINN ROUTP RAUX ROUTN MICROPHONE MICBIAS PLL SERIAL DATA I2C/SPI BIAS INPUT/OUTPUT PORTS CONTROL PORT MCLK ADC_SDATA K K DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
001
CLATCH CDATA CCLK COUT BCL RCL L
07679- Figure 1.
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/ Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) Outline Dimensions Ordering Guide