Datasheet AD1937 (Analog Devices) - 8

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AD1937 TIMING SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 8. Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC/ADC clock source = PLL clock 40 60 % @ 256 fS, 384 fS, 512 fS, and 768 fS tMH DAC/ADC clock source = direct MCLK 40 60 % @ 512 fS (bypass on-chip PLL) fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR Low 15 ns tPDRR Recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK or LRCLK 10 ms 256 fS VCO Clock, Output Duty Cycle, 40 60 % MCLKO/MCLKXO Pin I2C See Figure 13 and Figure 14 fSCL SCL clock frequency 400 kHz tSCLL SCL low 1.3 μs tSCLH SCL high 0.6 μs tSCS Setup time (start condition) Relevent for repeated start condition 0.6 μs tSCH Hold time (start condition) First clock generated after this period 0.6 μs tSSH Setup time (stop condition) 0.6 μs tDS Data setup time 100 ns tSR SDA and SCL rise time 300 ns tSF SDA and SCL fall time 300 ns tBFT Bus-free time Between stop and start 1.3 μs DAC SERIAL PORT See Figure 2 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns ADC SERIAL PORT See Figure 3 tABH ABCLK high Slave mode 10 ns tABL ABCLK low Slave mode 10 ns tALS ALRCLK setup To ABCLK rising, slave mode 10 ns ALRCLK skew From ABCLK falling, master mode −8 +8 ns tALH ALRCLK hold From ABCLK rising, slave mode 5 ns tABDD ASDATA delay From ABCLK falling, any mode 18 ns AUXILIARY INTERFACE tAXDS AAUXDATA setup To AUXBCLK rising 10 ns tAXDH AAUXDATA hold From AUXBCLK rising 5 ns tDXDD DAUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns Rev. B | Page 8 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TEST CONDITIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL OSCILLATOR SPECIFICATIONS DIGITAL SPECIFICATIONS POWER SUPPLY SPECIFICATIONS DIGITAL FILTERS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCs) DIGITAL-TO-ANALOG CONVERTERS (DACs) CLOCK SIGNALS RESET AND POWER-DOWN I2C CONTROL PORT POWER SUPPLY AND VOLTAGE REFERENCE SERIAL DATA PORTS—DATA FORMAT TIME-DIVISION MULTIPLEXED (TDM) MODES DAISY-CHAIN MODE ADDITIONAL MODES CONTROL REGISTERS DEFINITIONS PLL AND CLOCK CONTROL REGISTERS DAC CONTROL REGISTERS ADC CONTROL REGISTERS APPLICATIONS CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS