Datasheet SSM2603 (Analog Devices) - 3

link to page 4
Data Sheet SSM2603 SPECIFICATIONS
TA = 25°C, AVDD = DVDD = 3.3 V, HPVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Conditions
RECOMMENDED OPERATING CONDITIONS Analog Voltage Supply (AVDD) 1.8 3.3 3.6 V Digital Core Power Supply 1.5 3.3 3.6 V Digital I/O Supply 1.8 3.3 3.6 Ground (AGND, PGND, DGND) 0 V POWER CONSUMPTION Power-Up Stereo Record (1.5 V and 1.8 V) 7 mW Stereo Record (3.3 V) 22 mW Stereo Playback (1.5 V and 1.8 V) 7 mW Stereo Playback (3.3 V) 22 mW Power-Down 40 μW LINE INPUT Input Signal Level (0 dB) 1 × AVDD/3.3 V rms Input Impedance 200 kΩ PGA gain = 0 dB 10 kΩ PGA gain = +33 dB 480 kΩ PGA gain = −34.5 dB Input Capacitance 10 pF Signal-to-Noise Ratio (A-Weighted) 70 90 dB PGA gain = 0 dB, AVDD = 3.3 V 84 dB PGA gain = 0 dB, AVDD = 1.8 V THD + N −80 dB −1 dBFS input, AVDD = 3.3 V −75 dB −1 dBFS input, AVDD = 1.8 V Channel Separation 80 dB Programmable Gain −34.5 0 +33 dB Gain Step 1.5 dB Mute Attenuation −80 dB MICROPHONE INPUT Input Signal Level 1 × AVDD/3.3 V rms Signal-to-Noise Ratio (A-Weighted) 85 dB Microphone gain = 0 dB (REXT = 40 kΩ) Total Harmonic Distortion −70 dB −1 dBFS input, 0 dB gain Power Supply Rejection Ratio 50 dB Mute Attenuation 80 dB Input Resistance 10 kΩ Input Capacitance 10 pF MICROPHONE BIAS Bias Voltage 0.75 × AVDD V Bias Current Source 3 mA Noise in the Signal Bandwidth 40 nV/√Hz 20 Hz to 20 kHz LINE OUTPUT1 Full-Scale Output 1 × AVDD/3.3 V rms Signal-to-Noise Ratio (A-Weighted) 85 100 dB AVDD = 3.3 V 94 AVDD = 1.8 V THD + N −80 −70 dB AVDD = 3.3 V −75 AVDD = 1.8 V Power Supply Rejection Ratio 50 dB Channel Separation 80 dB Rev. D | Page 3 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide