Datasheet AD1939 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec |
| 页数 / 页 | 32 / 6 — AD1939. Data Sheet. DIGITAL FILTERS Table 6. Parameter. Mode. Factor. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 490 Kb |
| 文件语言 | 英语 |
AD1939. Data Sheet. DIGITAL FILTERS Table 6. Parameter. Mode. Factor. Min. Typ. Max. Unit. TIMING SPECIFICATIONS. Table 7. Parameter
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AD1939 Data Sheet DIGITAL FILTERS Table 6. Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER All modes, typical @ 48 kHz Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844/fS 479 µs DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 µs 96 kHz mode, typical @ 96 kHz 11/fS 115 µs 192 kHz mode, typical @ 192 kHz 8/fS 42 µs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 7. Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384 40 60 % fS, 512 fS, and 768 fS tMH DAC/ADC clock source = direct MCLK @ 512 fS 40 60 % (bypass on-chip PLL) fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR Low 15 ns tPDRR Recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock, Output Duty Cycle, 40 60 % MCLKO/XO Pin Rev. E | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide Automotive Products
ADC DECIMATION FILTER All modes, typical @ 48 kHz Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844/fS 479 µs DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 µs 96 kHz mode, typical @ 96 kHz 11/fS 115 µs 192 kHz mode, typical @ 192 kHz 8/fS 42 µs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 7. Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384 40 60 % fS, 512 fS, and 768 fS tMH DAC/ADC clock source = direct MCLK @ 512 fS 40 60 % (bypass on-chip PLL) fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR Low 15 ns tPDRR Recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock, Output Duty Cycle, 40 60 % MCLKO/XO Pin Rev. E | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide Automotive Products