Datasheet ADAV803 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Audio Codec for Recordable DVD |
| 页数 / 页 | 60 / 2 — ADAV803. TABLE OF CONTENTS. REVISION HISTORY. 7/07—Rev. 0 to Rev. A. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
ADAV803. TABLE OF CONTENTS. REVISION HISTORY. 7/07—Rev. 0 to Rev. A. 7/04—Revision 0: Initial Version
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ADAV803 TABLE OF CONTENTS
Features .. 1 DAC Section.. 18 Functional Block Diagram .. 1 Sample Rate Converter (SRC) Functional Overview .. 19 Applications... 1 PLL Section ... 22 General Description ... 1 S/PDIF Transmitter and Receiver .. 23 Revision History ... 2 Serial Data Ports ... 27 Specifications... 3 Interface Control .. 30 Test Conditions... 3 I2C Interface .. 30 ADAV803 Specifications ... 3 Block Reads and Writes ... 31 Timing Specifications .. 7 Register Descriptions ... 32 Temperature Range .. 7 Layout Considerations... 59 Absolute Maximum Ratings.. 8 ADC ... 59 ESD Caution.. 8 DAC.. 59 Pin Configuration and Function Descriptions... 9 PLL ... 59 Typical Performance Characteristics ... 11 Reset and Power-Down Considerations ... 59 Functional Description .. 15 Outline Dimensions ... 60 ADC Section ... 15 Ordering Guide .. 60
REVISION HISTORY 7/07—Rev. 0 to Rev. A
Changes to Table 1.. 3 Changes to ADC Section ... 15 Changes to Figure 25.. 15 Changes to Figure 33.. 21 Changes to SRC Architecture Section ... 21 Changes to Table 7.. 22 Changes to Figure 36.. 22 Changes to Figure 39, Figure 40, Figure 41, Figure 42 .. 23 Changes to Transmitter Operation Section .. 27 Changes to Interrupts Section .. 27 Changes to Figure 50.. 28 Changes to Table 97.. 47 Changes to Table 101.. 48 Changes to Table 136 and Table 137 .. 56 Updated Outline Dimensions ... 60 Changes to Ordering Guide .. 60
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 60 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TEST CONDITIONS ADAV803 SPECIFICATIONS TIMING SPECIFICATIONS TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION ADC SECTION Programmable Gain Amplifier (PGA) Analog Σ-Δ Modulator Automatic Level Control (ALC) Attack Mode No Recovery Mode Normal Recovery Mode Limited Recovery Mode Selecting a Sample Rate DAC SECTION Selecting a Sample Rate SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW Conceptual High Interpolation Model Hardware Model SRC Architecture PLL SECTION S/PDIF TRANSMITTER AND RECEIVER Serial Digital Audio Transmission Standards Receiver Section Transmitter Operation Autobuffering Interrupts SERIAL DATA PORTS Clocking Scheme Datapath INTERFACE CONTROL I2C INTERFACE BLOCK READS AND WRITES REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) S/PDIF Loopback Control—Address 0000011 (0x03) Playback Port Control—Address 0000100 (0x04) Auxiliary Input Port—Address 0000101 (0x05) Record Port Control—Address 0000110 (0x06) Auxiliary Output Port—Address 0000111 (0x07) Group Delay and Mute—Address 0001000 (0x08) Receiver Configuration 1—Address 0001001 (0x09) Receiver Configuration 2—Address 0001010 (0x0A) Receiver Buffer Configuration—Address 0001011 (0x0B) Transmitter Control—Address 0001100 (0x0C) Transmitter Buffer Configuration—Address 0001101 (0x0D) Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E) Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10) Autobuffer—Address 0010001 (0x11) Sample Rate Ratio MSB—Address 0010010 (0x12) Sample Rate Ratio LSB—Address 0010011 (0x13) Preamble-C MSB—Address 0010100 (0x14) Preamble-C LSB—Address 0010101 (0x15) Preamble-D MSB—Address 0010110 (0x16) Preamble-D LSB—Address 0010111 (0x17) Receiver Error—Address 0011000 (0x18) Receiver Error Mask—Address 0011001 (0x19) Sample Rate Converter Error—Address 0011010 (0x1A) Sample Rate Converter Error Mask—Address 0011011 (0x1B) Interrupt Status—Address 0011100 (0x1C) Interrupt Status Mask—Address 0011101 (0x1D) Mute and De-Emphasis—Address 0011110 (0x1E) NonAudio Preamble Type—Address 0011111 (0x1F) Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37) Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F) Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Receiver User Bit Buffer Data—Address 1010001 (0x51) Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52) Transmitter User Bit Buffer Data—Address 1010011 (0x53) Q Subcode CRCError Status—Address 1010100 (0x54) Q Subcode Buffer—Address 0x55 to Address 0x5E Datapath Control Register 1—Address 1100010 (0x62) Datapath Control Register 2—Address 1100011 (0x63) DAC Control Register 1—Address 1100100 (0x64) DAC Control Register 2—Address 1100101 (0x65) DAC Control Register 3—Address 1100110 (0x66) DAC Control Register 4—Address 1100111 (0x67) DAC Left Volume—Address 1101000 (0x68) DAC Right Volume—Address 1101001 (0x69) DAC Left Peak Volume—Address 1101010 (0x6A) DAC Right Peak Volume—Address 1101011 (0x6B) ADC Left Channel PGA Gain—Address 1101100 (0x6C) ADC Right Channel PGA Gain—Address 1101101 (0x6D) ADC Control Register 1—Address 1101110 (0x6E) ADC Control Register 2—Address 1101111 (0x6F) ADC Left Volume—Address 1110000 (0x70) ADC Right Volume—Address 1110001 (0x71) ADC Left Peak Volume—Address 1110010 (0x72) ADC Right Peak Volume—Address 1110011 (0x73) PLL Control Register 1—Address 1110100 (0x74) PLL Control Register 2—Address 1110101 (0x75) Internal Clocking Control Register 1—Address 1110110 (0x76) Internal Clocking Control Register 2—Address 1110111 (0x77) PLL Clock Source Register—Address 1111000 (0x78) PLL Output Enable—Address 1111010 (0x7A) ALC Control Register 1—Address 1111011 (0x7B) ALC Control Register 2— Address = 1111100 (0x7C) ALC Control Register 3—Address 1111101 (0x7D) LAYOUT CONSIDERATIONS ADC DAC PLL RESET AND POWER-DOWN CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADAV803 TABLE OF CONTENTS
Features .. 1 DAC Section.. 18 Functional Block Diagram .. 1 Sample Rate Converter (SRC) Functional Overview .. 19 Applications... 1 PLL Section ... 22 General Description ... 1 S/PDIF Transmitter and Receiver .. 23 Revision History ... 2 Serial Data Ports ... 27 Specifications... 3 Interface Control .. 30 Test Conditions... 3 I2C Interface .. 30 ADAV803 Specifications ... 3 Block Reads and Writes ... 31 Timing Specifications .. 7 Register Descriptions ... 32 Temperature Range .. 7 Layout Considerations... 59 Absolute Maximum Ratings.. 8 ADC ... 59 ESD Caution.. 8 DAC.. 59 Pin Configuration and Function Descriptions... 9 PLL ... 59 Typical Performance Characteristics ... 11 Reset and Power-Down Considerations ... 59 Functional Description .. 15 Outline Dimensions ... 60 ADC Section ... 15 Ordering Guide .. 60
REVISION HISTORY 7/07—Rev. 0 to Rev. A
Changes to Table 1.. 3 Changes to ADC Section ... 15 Changes to Figure 25.. 15 Changes to Figure 33.. 21 Changes to SRC Architecture Section ... 21 Changes to Table 7.. 22 Changes to Figure 36.. 22 Changes to Figure 39, Figure 40, Figure 41, Figure 42 .. 23 Changes to Transmitter Operation Section .. 27 Changes to Interrupts Section .. 27 Changes to Figure 50.. 28 Changes to Table 97.. 47 Changes to Table 101.. 48 Changes to Table 136 and Table 137 .. 56 Updated Outline Dimensions ... 60 Changes to Ordering Guide .. 60
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 60 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TEST CONDITIONS ADAV803 SPECIFICATIONS TIMING SPECIFICATIONS TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION ADC SECTION Programmable Gain Amplifier (PGA) Analog Σ-Δ Modulator Automatic Level Control (ALC) Attack Mode No Recovery Mode Normal Recovery Mode Limited Recovery Mode Selecting a Sample Rate DAC SECTION Selecting a Sample Rate SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW Conceptual High Interpolation Model Hardware Model SRC Architecture PLL SECTION S/PDIF TRANSMITTER AND RECEIVER Serial Digital Audio Transmission Standards Receiver Section Transmitter Operation Autobuffering Interrupts SERIAL DATA PORTS Clocking Scheme Datapath INTERFACE CONTROL I2C INTERFACE BLOCK READS AND WRITES REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) S/PDIF Loopback Control—Address 0000011 (0x03) Playback Port Control—Address 0000100 (0x04) Auxiliary Input Port—Address 0000101 (0x05) Record Port Control—Address 0000110 (0x06) Auxiliary Output Port—Address 0000111 (0x07) Group Delay and Mute—Address 0001000 (0x08) Receiver Configuration 1—Address 0001001 (0x09) Receiver Configuration 2—Address 0001010 (0x0A) Receiver Buffer Configuration—Address 0001011 (0x0B) Transmitter Control—Address 0001100 (0x0C) Transmitter Buffer Configuration—Address 0001101 (0x0D) Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E) Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10) Autobuffer—Address 0010001 (0x11) Sample Rate Ratio MSB—Address 0010010 (0x12) Sample Rate Ratio LSB—Address 0010011 (0x13) Preamble-C MSB—Address 0010100 (0x14) Preamble-C LSB—Address 0010101 (0x15) Preamble-D MSB—Address 0010110 (0x16) Preamble-D LSB—Address 0010111 (0x17) Receiver Error—Address 0011000 (0x18) Receiver Error Mask—Address 0011001 (0x19) Sample Rate Converter Error—Address 0011010 (0x1A) Sample Rate Converter Error Mask—Address 0011011 (0x1B) Interrupt Status—Address 0011100 (0x1C) Interrupt Status Mask—Address 0011101 (0x1D) Mute and De-Emphasis—Address 0011110 (0x1E) NonAudio Preamble Type—Address 0011111 (0x1F) Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37) Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F) Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Receiver User Bit Buffer Data—Address 1010001 (0x51) Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52) Transmitter User Bit Buffer Data—Address 1010011 (0x53) Q Subcode CRCError Status—Address 1010100 (0x54) Q Subcode Buffer—Address 0x55 to Address 0x5E Datapath Control Register 1—Address 1100010 (0x62) Datapath Control Register 2—Address 1100011 (0x63) DAC Control Register 1—Address 1100100 (0x64) DAC Control Register 2—Address 1100101 (0x65) DAC Control Register 3—Address 1100110 (0x66) DAC Control Register 4—Address 1100111 (0x67) DAC Left Volume—Address 1101000 (0x68) DAC Right Volume—Address 1101001 (0x69) DAC Left Peak Volume—Address 1101010 (0x6A) DAC Right Peak Volume—Address 1101011 (0x6B) ADC Left Channel PGA Gain—Address 1101100 (0x6C) ADC Right Channel PGA Gain—Address 1101101 (0x6D) ADC Control Register 1—Address 1101110 (0x6E) ADC Control Register 2—Address 1101111 (0x6F) ADC Left Volume—Address 1110000 (0x70) ADC Right Volume—Address 1110001 (0x71) ADC Left Peak Volume—Address 1110010 (0x72) ADC Right Peak Volume—Address 1110011 (0x73) PLL Control Register 1—Address 1110100 (0x74) PLL Control Register 2—Address 1110101 (0x75) Internal Clocking Control Register 1—Address 1110110 (0x76) Internal Clocking Control Register 2—Address 1110111 (0x77) PLL Clock Source Register—Address 1111000 (0x78) PLL Output Enable—Address 1111010 (0x7A) ALC Control Register 1—Address 1111011 (0x7B) ALC Control Register 2— Address = 1111100 (0x7C) ALC Control Register 3—Address 1111101 (0x7D) LAYOUT CONSIDERATIONS ADC DAC PLL RESET AND POWER-DOWN CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE