Datasheet ADAV801 (Analog Devices)

Audio Codec for Recordable DVD ADAV801 FEATURES FUNCTIONAL BLOCK DIAGRAM 1 2 3 Stereo analog-to-digital converter (ADC) I O LK LK LK CH T K K U L L SC SC SC UT K T A Supports 48 kHz/96 kHz sample rates N XIN XO MC MC SY SY SY CO CI CCL CL 102 dB dynamic range Single-ended input PLL CONTROL REGISTERS Automatic level control VINL OLRCLK Stereo digital-to-analog converter (DAC) ANALOG-TO-DIGITAL RECORD CONVERTER DATA VINR OBCLK OUTPUT Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz OSDATA VREF REFERENCE SRC DIGITAL sample rates INPUT/OUTPUT OAUXLRCLK AUX DATA SWITCHING MATRIX OUTPUT OAUXBCLK 101 dB dynamic range (DATAPATH) VOUTL OAUXSDATA DIGITAL-TO-ANALOG Single-ended output VOUTR CONVERTER DIT DITOUT Asynchronous operation of ADC and DAC FILTD Stereo sample rate converter (SRC) PLAYBACK AUX DATA ZEROL/INT DIR DATA INPUT INPUT ZEROR Input/output range: 8 kHz to 192 kHz ADAV801 140 dB dynamic range Digital interfaces K K K K L TA TA N C A A RI RCL D RCL BCL D DI IB Record IS L IL X S X
001
UX IAU U IA Playback IA
04577- Figure 1.
Auxiliary record Auxiliary playback APPLICATIONS S/PDIF (IEC 60958) input and output DVD-recordable Digital interface receiver (DIR) All formats Digital interface transmitter (DIT) CD-R/W PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via SPI-compatible serial port 64-lead LQFP package GENERAL DESCRIPTION
The ADAV801 is a stereo audio codec intended for applications The sample rate converter (SRC) provides high performance such as DVD or CD recorders that require high performance sample rate conversion to allow inputs and outputs that require and flexible, cost-effective playback and record functionality. different sample rates to be matched. The SRC input can be The ADAV801 features Analog Devices, Inc. proprietary, high selected from playback, auxiliary, DIR, or ADC (record). The performance converter cores to provide record (ADC), playback SRC output can be applied to the playback DAC, both main and (DAC), and format conversion (SRC) on a single chip. The auxiliary record channels, and a DIT. ADAV801 record channel features variable input gain to allow Operation of the ADAV801 is controlled via an SPI-compatible for adjustment of recorded input levels and automatic level serial interface, which allows the programming of individual control, followed by a high performance stereo ADC whose control register settings. The ADAV801 operates from a single digital output is sent to the record interface. The record channel analog 3.3 V power supply and a digital power supply of 3.3 V also features level detectors that can be used in feedback loops with an optional digital interface range of 3.0 V to 3.6 V. to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with The part is housed in a 64-lead LQFP package and is character- independent digital volume control. ized for operation over the commercial temperature range of −40°C to +85°C.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TEST CONDITIONS ADAV801 SPECIFICATIONS TIMING SPECIFICATIONS TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION ADC SECTION Programmable Gain Amplifier (PGA) Analog Σ-Δ Modulator Automatic Level Control (ALC) Attack Mode No Recovery Mode Normal Recovery Mode Limited Recovery Mode Selecting a Sample Rate DAC SECTION Selecting a Sample Rate SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW Conceptual High Interpolation Model Hardware Model SRC Architecture PLL SECTION S/PDIF TRANSMITTER AND RECEIVER Serial Digital Audio Transmission Standards Receiver Section Transmitter Operation Autobuffering Interrupts SERIAL DATA PORTS Clocking Scheme Datapath INTERFACE CONTROL SPI INTERFACE BLOCK READS AND WRITES REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) S/PDIF Loopback Control—Address 0000011 (0x03) Playback Port Control—Address 0000100 (0x04) Auxiliary Input Port—Address 0000101 (0x05) Record Port Control—Address 0000110 (0x06) Auxiliary Output Port—Address 0000111 (0x07) Group Delay and Mute—Address 0001000 (0x08) Receiver Configuration 1—Address 0001001 (0x09) Receiver Configuration 2—Address 0001010 (0x0A) Receiver Buffer Configuration—Address 0001011 (0x0B) Transmitter Control—Address 0001100 (0x0C) Transmitter Buffer Configuration—Address 0001101 (0x0D) Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E) Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10) Autobuffer—Address 0010001 (0x11) Sample Rate Ratio MSB—Address 0010010 (0x12) Sample Rate Ratio LSB—Address 0010011 (0x13) Preamble-C MSB—Address 0010100 (0x14) Preamble-C LSB—Address 0010101 (0x15) Preamble-D MSB—Address 0010110 (0x16) Preamble-D LSB—Address 0010111 (0x17) Receiver Error—Address 0011000 (0x18) Receiver Error Mask—Address 0011001 (0x19) Sample Rate Converter Error—Address 0011010 (0x1A) Sample Rate Converter Error Mask—Address 0011011 (0x1B) Interrupt Status—Address 0011100 (0x1C) Interrupt Status Mask—Address 0011101 (0x1D) Mute and De-Emphasis—Address 0011110 (0x1E) NonAudio Preamble Type—Address 0011111 (0x1F) Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37) Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F) Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Receiver User Bit Buffer Data—Address 1010001 (0x51) Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52) Transmitter User Bit Buffer Data—Address 1010011 (0x53) Q Subcode CRCError Status—Address 1010100 (0x54) Q Subcode Buffer—Address 0x55 to Address 0x5E Datapath Control Register 1—Address 1100010 (0x62) Datapath Control Register 2—Address 1100011 (0x63) DAC Control Register 1—Address 1100100 (0x64) DAC Control Register 2—Address 1100101 (0x65) DAC Control Register 3—Address 1100110 (0x66) DAC Control Register 4—Address 1100111 (0x67) DAC Left Volume—Address 1101000 (0x68) DAC Right Volume—Address 1101001 (0x69) DAC Left Peak Volume—Address 1101010 (0x6A) DAC Right Peak Volume—Address 1101011 (0x6B) ADC Left Channel PGA Gain—Address 1101100 (0x6C) ADC Right Channel PGA Gain—Address 1101101 (0x6D) ADC Control Register 1—Address 1101110 (0x6E) ADC Control Register 2—Address 1101111 (0x6F) ADC Left Volume—Address 1110000 (0x70) ADC Right Volume—Address 1110001 (0x71) ADC Left Peak Volume—Address 1110010 (0x72) ADC Right Peak Volume—Address 1110011 (0x73) PLL Control Register 1—Address 1110100 (0x74) PLL Control Register 2—Address 1110101 (0x75) Internal Clocking Control Register 1—Address 1110110 (0x76) Internal Clocking Control Register 2—Address 1110111 (0x77) PLL Clock Source Register—Address 1111000 (0x78) PLL Output Enable—Address 1111010 (0x7A) ALC Control Register 1—Address 1111011 (0x7B) ALC Control Register 2— Address = 1111100 (0x7C) ALC Control Register 3—Address 1111101 (0x7D) LAYOUT CONSIDERATIONS ADC DAC PLL RESET AND POWER-DOWN CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE