Datasheet AD73322L (Analog Devices) - 7

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AD73322L SIGNAL RANGES Table 3. Mnemoic Description Range
VREFCAP 1.2 V ± 10% VREFOUT 1.2 V ± 10% ADC Maximum input range at VIN 1.578 V p-p Nominal reference level 1.0954 V p-p DAC Maximum voltage output swing Single-Ended 1.578 V p-p Differential 3.156 V p-p Nominal voltage output swing Single-Ended 1.0954 V p-p Differential 2.1909 V p-p Output bias voltage VREFOUT
TIMING CHARACTERISTICS
AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted.
Table 4. Parameter Limit at TA = −40°C to +105°C Unit Description
Clock Signals See Figure 2 t1 61 ns min MCLK period t2 24.4 ns min MCLK width high t3 24.4 ns min MCLK width low Serial Port See Figure 4 and Figure 5 t4 t1 ns min SCLK period t5 0.4 × t1 ns min SCLK width high t6 0.4 × t1 ns min SCLK width low t7 20 ns min SDI/SDIFS setup before SCLK low t8 0 ns min SDI/SDIFS hold after SCLK low t9 10 ns max SDOFS delay from SCLK high t10 10 ns min SDOFS hold after SCLK high t11 10 ns min SDO hold after SCLK high t12 10 ns max SDO delay from SCLK high t13 30 ns max SCLK delay from MCLK Rev. A | Page 7 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE