Datasheet AD73322 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 页数 / 页 | 43 / 2 — AD73322–SPECIFICATIONS1 (AVDD = +3 V. 10%; DVDD = +3 V. 10%; DGND = AGND … |
| 修订版 | B |
| 文件格式/大小 | PDF / 396 Kb |
| 文件语言 | 英语 |
AD73322–SPECIFICATIONS1 (AVDD = +3 V. 10%; DVDD = +3 V. 10%; DGND = AGND = 0 V, fDMCLK =
该数据表的模型线
文件文字版本
AD73322–SPECIFICATIONS1 (AVDD = +3 V
ⴞ
10%; DVDD = +3 V
ⴞ
10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) AD73322A Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE 5VEN = 0 REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFOUT REFCAP to AGND2 Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.08 1.2 1.32 V Unloaded Minimum Load Resistance 1 kΩ Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 1.578 V Max Output Swing = (1.578/1.2) × VREFCAP Feedback Resistance 50 Ω fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 5 Bits Gain Step Size = 0.0625 Gain Accuracy ±1.0 % Output Unloaded Settling Time 1.0 µs Tap Gain Change of –FS to +FS Delay 0.5 µs ADC SPECIFICATIONS 5VEN = 0 Maximum Input Range at VIN2, 3 1.578 V p-p Measured Differentially –2.85 dBm Max Input = (1.578/1.2) × VREFCAP Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially (0 dBm0) –6.02 dBm Absolute Gain PGA = 0 dB –0.5 0.4 +1.2 dB 1.0 kHz, 0 dBm0 PGA = 38 dB –1.5 –0.7 +0.1 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 Signal to (Noise + Distortion) Refer to Figure 5 PGA = 0 dB 72 78 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz 55 57 dB 0 Hz to fSAMP/2; fSAMP = 64 kHz PGA = 38 dB 52 56 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Total Harmonic Distortion PGA = 0 dB –84 –73 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA = 38 dB –70 –60 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Intermodulation Distortion –65 dB PGA = 0 dB Idle Channel Noise –71 dBm0 PGA = 0 dB Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed –70 dB Input Amplifiers Included in Input Channel DC Offset –30 +10 +45 mV PGA = 0 dB Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave Group Delay4, 5 25 µs Input Resistance at PGA2, 4, 6 20 kΩ Input Amplifiers Bypassed DIGITAL GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 16 Bits Tested to 5 MSBs of Settings Delay 25 µs Includes DAC Delay Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes DAC Settling Time –2– REV. B
ⴞ
10%; DVDD = +3 V
ⴞ
10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) AD73322A Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE 5VEN = 0 REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFOUT REFCAP to AGND2 Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.08 1.2 1.32 V Unloaded Minimum Load Resistance 1 kΩ Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 1.578 V Max Output Swing = (1.578/1.2) × VREFCAP Feedback Resistance 50 Ω fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 5 Bits Gain Step Size = 0.0625 Gain Accuracy ±1.0 % Output Unloaded Settling Time 1.0 µs Tap Gain Change of –FS to +FS Delay 0.5 µs ADC SPECIFICATIONS 5VEN = 0 Maximum Input Range at VIN2, 3 1.578 V p-p Measured Differentially –2.85 dBm Max Input = (1.578/1.2) × VREFCAP Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially (0 dBm0) –6.02 dBm Absolute Gain PGA = 0 dB –0.5 0.4 +1.2 dB 1.0 kHz, 0 dBm0 PGA = 38 dB –1.5 –0.7 +0.1 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 Signal to (Noise + Distortion) Refer to Figure 5 PGA = 0 dB 72 78 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz 55 57 dB 0 Hz to fSAMP/2; fSAMP = 64 kHz PGA = 38 dB 52 56 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Total Harmonic Distortion PGA = 0 dB –84 –73 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA = 38 dB –70 –60 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Intermodulation Distortion –65 dB PGA = 0 dB Idle Channel Noise –71 dBm0 PGA = 0 dB Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed –70 dB Input Amplifiers Included in Input Channel DC Offset –30 +10 +45 mV PGA = 0 dB Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave Group Delay4, 5 25 µs Input Resistance at PGA2, 4, 6 20 kΩ Input Amplifiers Bypassed DIGITAL GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 16 Bits Tested to 5 MSBs of Settings Delay 25 µs Includes DAC Delay Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes DAC Settling Time –2– REV. B