Datasheet AD73311 (Analog Devices) - 6

AD73311 Table II. Current Summary (AVDD = DVDD = +5.5 V) Analog Internal Digital External Interface MCLK Conditions Current Current Current Total Current SE ON Comments
ADC On Only 8.5 6 2 16.5 1 YES REFOUT Disabled ADC and DAC On 14.5 6 2 22.5 1 YES REFOUT Disabled REFCAP On Only 0.8 0 0 1.0 0 NO REFOUT Disabled REFCAP and REFOUT On Only 3.5 0 0 3.5 0 NO All Sections Off 0 1.5 0 1.7 0 YES MCLK Active Levels Equal to 0 V and DVDD All Sections Off 0 0.01 0 0.02 0 NO Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted.
Table III. Signal Ranges 3 V Power Supply 5 V Power Supply 5VEN = 0 5VEN = 0 5VEN = 1
VREFCAP 1.2 V ± 10% 1.2 V 2.4 V VREFOUT 1.2 V ± 10% 1.2 V 2.4 V ADC Maximum Input Range at VIN 1.578 V p-p 1.578 V p-p 3.156 V p-p Nominal Reference Level 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p DAC Maximum Voltage Output Swing Single-Ended 1.578 V p-p 1.578 V p-p 3.156 V p-p Differential 3.156 V p-p 3.156 V p-p 6.312 V p-p Nominal Voltage Output Swing Single-Ended 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p Differential 2.1909 V p-p 2.1909 V p-p 4.3818 V p-p Output Bias Voltage VREFOUT VREFOUT VREFOUT
(AVDD = +3 V
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10%; DVDD = +3 V
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10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
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C to +85
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C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK –6– REV. B