Datasheet PI6CB33202 (Diodes) - 2
| 制造商 | Diodes |
| 描述 | Very-Low-Power Two-Output PCIe Clock Buffer With On-Chip Termination |
| 页数 / 页 | 20 / 2 — PI6CB33202. Pin Configuration. GND. Pin Description. Pin Number Pin Name. … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
PI6CB33202. Pin Configuration. GND. Pin Description. Pin Number Pin Name. Type. Description
该数据表的模型线
文件文字版本
A product Line of Diodes Incorporated
PI6CB33202 Pin Configuration
OE[3:0]# Q3 BW_SEL_TRI SADR_TRI PD# VDDO NC OE1# Q2 IN+ PLL IN- 24 23 22 21 20 19 NC 1 18 Q1- Q1 NC 2 Q1+ 17 Q0 SCLK VDD_R 3 16 VDDA SDATA SADR_TRIIN+ 4 CTRL 15 OE0# BW_SEL_TRI LOGIC
GND
PD#IN- 5 14 Q0- GND_DIG 6 13 Q0+ 7 8 9 10 11 12 O ATA NC NC D _DIG SCLK S V DD V DD
Pin Description Pin Number Pin Name Type Description
1 NC — — Internal connected for feedback loop. Do not connect this pin. 2 NC — — Internal connected for feedback loop. Do not connect this pin. 3 VDD_R Power — Power supply for input differential buffers 4 IN+ Input — Differential true clock input 5 IN- Input — Differential complementary clock input 6 GND_DIG Power — Ground for digital circuitry 7 SDATA Input/ Output CMOS SMBUS data line, 3.3V tolerant 8 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 VDDO Power — Power supply for differential outputs 11 NC — — Do not connect this pin. 12 NC — — Do not connect this pin. 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output Active-low input for enabling Q0 pair. This pin has an internal pulldown. 15 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 16 VDDA Power — Power supply for analog circuitry 17 Q1+ Output HCSL Differential true clock output PI6CB33202 www.diodes.com January 2020 Document Number DS41834 Rev 5-2 2 Diodes Incorporated
PI6CB33202 Pin Configuration
OE[3:0]# Q3 BW_SEL_TRI SADR_TRI PD# VDDO NC OE1# Q2 IN+ PLL IN- 24 23 22 21 20 19 NC 1 18 Q1- Q1 NC 2 Q1+ 17 Q0 SCLK VDD_R 3 16 VDDA SDATA SADR_TRIIN+ 4 CTRL 15 OE0# BW_SEL_TRI LOGIC
GND
PD#IN- 5 14 Q0- GND_DIG 6 13 Q0+ 7 8 9 10 11 12 O ATA NC NC D _DIG SCLK S V DD V DD
Pin Description Pin Number Pin Name Type Description
1 NC — — Internal connected for feedback loop. Do not connect this pin. 2 NC — — Internal connected for feedback loop. Do not connect this pin. 3 VDD_R Power — Power supply for input differential buffers 4 IN+ Input — Differential true clock input 5 IN- Input — Differential complementary clock input 6 GND_DIG Power — Ground for digital circuitry 7 SDATA Input/ Output CMOS SMBUS data line, 3.3V tolerant 8 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 VDDO Power — Power supply for differential outputs 11 NC — — Do not connect this pin. 12 NC — — Do not connect this pin. 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output Active-low input for enabling Q0 pair. This pin has an internal pulldown. 15 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 16 VDDA Power — Power supply for analog circuitry 17 Q1+ Output HCSL Differential true clock output PI6CB33202 www.diodes.com January 2020 Document Number DS41834 Rev 5-2 2 Diodes Incorporated