Datasheet PI6CB33601 (Diodes) - 8
| 制造商 | Diodes |
| 描述 | Very Low Power 6-Output PCIe Clock Buffer With On-Chip Termination |
| 页数 / 页 | 20 / 8 — PI6CB33601. HCSL Output Characteristics. Symbol. Parameters. Condition. … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
PI6CB33601. HCSL Output Characteristics. Symbol. Parameters. Condition. Min. Typ. Max. Units. Note:. HCSL Output AC Characteristics
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PI6CB33601 HCSL Output Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
VOH Output Voltage High(1) Statistical measurement on single-ended 660 784 850 mV V signal using oscilloscope math function OL Output Voltage Low(1) -150 150 mV VOMAX Output Voltage Maximum(1) Measurement on single ended signal using 816 1150 mV V absolute value OMIN Output Voltage Minimum(1) -300 -42 mV VOC Output Cross Voltage(1,2,4) 250 430 550 mV DVOC VOC Magnitude Change(1,2,5) 12 140 mV
Note:
1. At default SMBUS amplitude settings 2. Guaranteed by design and characterization, not 100% tested in production 3. Measured from differential waveform 4. This one is defined as voltage where Q+ = Q- measured on a component test board and only applied to the differential rising edge 5. The total variation of all Vcross measurements in any particular system. This is a subset of Vcross_min/max allowed.
HCSL Output AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
fOUT Output Frequency 50 100 133.33 MHz -3dB point in High Bandwidth Mode 1.3 3.2 3.6 MHz BW PLL bandwidth(1,8) -3dB point in Low Bandwidth Mode 0.7 1.7 1.9 MHz tjpeak PLL Jitter Peaking(1) Peak pass band gain 0.8 2 dB Scope averaging on fast setting 2.5 3.2 4.0 V/ns tRF Slew rate(1,2,3) Scope averaging on slow setting 2.2 3.0 3.7 V/ns DtRF Slew rate matching(1,2,4) Scope averaging on 7 15 % tSKEW Output Skew(1,2) Averaging on, VT = 50% 21 50 ps PLL Bypass mode, VT = 50% 2000 2500 3000 ps tPDELAY Propagation delay PLL mode, VT = 50% -200 90 200 ps tDC Duty Cycle(1,2) Measured differentially, PLL Mode 45 50 55 % tDCD Duty Cycle Distortion(1,7) Measured differentially, PLL Bypass Mode at 100MHz -3.5 0 3.5 % tDCD Duty Cycle Distortion(1,7) Measured differentially, SE input, PLL Bypass Mode at 100MHz -10 0 10 % PLL mode 14 50 ps tjc-c Cycle to cycle jitter(1,2) Additive jitter, Bypass mode 0.1 1 ps PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 8 Diodes Incorporated
PI6CB33601 HCSL Output Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
VOH Output Voltage High(1) Statistical measurement on single-ended 660 784 850 mV V signal using oscilloscope math function OL Output Voltage Low(1) -150 150 mV VOMAX Output Voltage Maximum(1) Measurement on single ended signal using 816 1150 mV V absolute value OMIN Output Voltage Minimum(1) -300 -42 mV VOC Output Cross Voltage(1,2,4) 250 430 550 mV DVOC VOC Magnitude Change(1,2,5) 12 140 mV
Note:
1. At default SMBUS amplitude settings 2. Guaranteed by design and characterization, not 100% tested in production 3. Measured from differential waveform 4. This one is defined as voltage where Q+ = Q- measured on a component test board and only applied to the differential rising edge 5. The total variation of all Vcross measurements in any particular system. This is a subset of Vcross_min/max allowed.
HCSL Output AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
fOUT Output Frequency 50 100 133.33 MHz -3dB point in High Bandwidth Mode 1.3 3.2 3.6 MHz BW PLL bandwidth(1,8) -3dB point in Low Bandwidth Mode 0.7 1.7 1.9 MHz tjpeak PLL Jitter Peaking(1) Peak pass band gain 0.8 2 dB Scope averaging on fast setting 2.5 3.2 4.0 V/ns tRF Slew rate(1,2,3) Scope averaging on slow setting 2.2 3.0 3.7 V/ns DtRF Slew rate matching(1,2,4) Scope averaging on 7 15 % tSKEW Output Skew(1,2) Averaging on, VT = 50% 21 50 ps PLL Bypass mode, VT = 50% 2000 2500 3000 ps tPDELAY Propagation delay PLL mode, VT = 50% -200 90 200 ps tDC Duty Cycle(1,2) Measured differentially, PLL Mode 45 50 55 % tDCD Duty Cycle Distortion(1,7) Measured differentially, PLL Bypass Mode at 100MHz -3.5 0 3.5 % tDCD Duty Cycle Distortion(1,7) Measured differentially, SE input, PLL Bypass Mode at 100MHz -10 0 10 % PLL mode 14 50 ps tjc-c Cycle to cycle jitter(1,2) Additive jitter, Bypass mode 0.1 1 ps PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 8 Diodes Incorporated