Datasheet PI6CB33401 (Diodes) - 2
| 制造商 | Diodes |
| 描述 | Very Low Power 4-Output PCIe Clock Buffer With On-Chip Termination |
| 页数 / 页 | 20 / 2 — PI6CB33401. Pin Configuration. GND. Pin Description. Pin Number Pin Name. … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
PI6CB33401. Pin Configuration. GND. Pin Description. Pin Number Pin Name. Type. Description
该数据表的模型线
文件文字版本
A product Line of Diodes Incorporated
PI6CB33401 Pin Configuration
OE[3:0]# O SADR_TRI PD# NC OE3# Q3- Q3+ NC V DD Q3 32 31 30 29 28 27 26 25 Q2 IN+ BW_SEL_TRI 1 PLL 24 OE2# IN- NC 2 23 Q2- Q1 NC 3 22 Q2+ Q0 SCLK VDD_R 4 21 VDDA SDATA
GND
IN+ 5 20 NC SADR_TRI CTRL BW_SEL_TRI IN- 6 LOGIC 19 OE1# PD# NC 7 Q1- 18 GND_DIG 8 17 Q1+ 9 10 11 12 13 14 15 16 O ATA Q0+ Q0- NC SCLK D _DIG OE0# S V DD V DD
Pin Description Pin Number Pin Name Type Description
1 BW_SEL_TRI Input Tri-level Latch to select low loop bandwidth, bypass PLL, and high loop band- width. This pin has both internal pull-up and pull-down 2 NC Internal connected for feedback loop. Do not connect this pin 3 NC Internal connected for feedback loop. Do not connect this pin 4 VDD_R Power Power supply for input differential buffers 5 IN+ Input Differential true clock input 6 IN- Input Differential complementary clock input 7 NC Do not connect this pin 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15, 25 VDDO Power Power supply for differential outputs 16 NC Do not connect this pin 17 Q1+ Output HCSL Differential true clock output 18 Q1- Output HCSL Differential complementary clock output PI6CB33401 www.diodes.com January 2020 Document Number DS41292 Rev 5-2 2 Diodes Incorporated
PI6CB33401 Pin Configuration
OE[3:0]# O SADR_TRI PD# NC OE3# Q3- Q3+ NC V DD Q3 32 31 30 29 28 27 26 25 Q2 IN+ BW_SEL_TRI 1 PLL 24 OE2# IN- NC 2 23 Q2- Q1 NC 3 22 Q2+ Q0 SCLK VDD_R 4 21 VDDA SDATA
GND
IN+ 5 20 NC SADR_TRI CTRL BW_SEL_TRI IN- 6 LOGIC 19 OE1# PD# NC 7 Q1- 18 GND_DIG 8 17 Q1+ 9 10 11 12 13 14 15 16 O ATA Q0+ Q0- NC SCLK D _DIG OE0# S V DD V DD
Pin Description Pin Number Pin Name Type Description
1 BW_SEL_TRI Input Tri-level Latch to select low loop bandwidth, bypass PLL, and high loop band- width. This pin has both internal pull-up and pull-down 2 NC Internal connected for feedback loop. Do not connect this pin 3 NC Internal connected for feedback loop. Do not connect this pin 4 VDD_R Power Power supply for input differential buffers 5 IN+ Input Differential true clock input 6 IN- Input Differential complementary clock input 7 NC Do not connect this pin 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15, 25 VDDO Power Power supply for differential outputs 16 NC Do not connect this pin 17 Q1+ Output HCSL Differential true clock output 18 Q1- Output HCSL Differential complementary clock output PI6CB33401 www.diodes.com January 2020 Document Number DS41292 Rev 5-2 2 Diodes Incorporated