Datasheet PI6CB33801 (Diodes) - 2
| 制造商 | Diodes |
| 描述 | Very-Low-Power 8-Output PCIe Clock Buffer with On-Chip Termination |
| 页数 / 页 | 21 / 2 — PI6CB33801. Pin Configuration. GND. Pin Description. Pin Number Pin Name. … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
PI6CB33801. Pin Configuration. GND. Pin Description. Pin Number Pin Name. Type. Description
该数据表的模型线
文件文字版本
A product Line of Diodes Incorporated
PI6CB33801 Pin Configuration
O O OE[7:0]# PD# V DD OE7# Q7- Q7+ OE6# Q6- Q6+ GND V DD V DD OE5# Q7 48 47 46 45 44 43 42 41 40 39 38 37 SADR_TRI 1 Q6 36 Q5- IN+ PLL IN- BW_SEL_TRI 2 35 Q5+ Q5 NC 3 34 OE4# NC 4 33 Q4- Q4 VDD_R 5 32 Q4+ SCLK IN+ 6 Q3 31 VDDO
GND
SDATA IN- 7 30 VDDA SADR_TRI CTRL BW_SEL_TRI LOGIC GND_R 8 Q2 29 GNDA PD# GND_DIG 9 28 OE3# Q1 SCLK 10 27 Q3- SDATA 11 26 Q3+ Q0 VDD_DIG 12 25 OE2# 13 14 15 16 17 18 19 20 21 22 23 24 O O Q0+ Q0- Q1+ Q1- V DD OE0# VDD OE1# Q2+ V DD GND Q2-
Pin Description Pin Number Pin Name Type Description
1 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down. 2 BW_SEL_TRI Input Tri-level Latch to select low-loop bandwidth, bypass PLL, and high-loop band- width. This pin has both internal pull-up and pull-down. 3 NC — — Internal connected for feedback loop. Do not connect this pin. 4 NC — — Internal connected for feedback loop. Do not connect this pin. 5 VDD_R Power — Power supply for input differential buffers 6 IN+ Input — Differential true clock input 7 IN- Input — Differential complementary clock input 8 GND_R Power — Ground for input differential buffers 9 GND_DIG Power — Ground for digital circuitry 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 11 SDATA Input/ Output CMOS SMBUS data line, 3.3V tolerant 12 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 13, 21, 31, 39, 47 VDDO Power — Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 14 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 15 Q0+ Output HCSL Differential true clock output PI6CB33801 www.diodes.com January 2020 Document Number DS41288 Rev 5-2 2 Diodes Incorporated
PI6CB33801 Pin Configuration
O O OE[7:0]# PD# V DD OE7# Q7- Q7+ OE6# Q6- Q6+ GND V DD V DD OE5# Q7 48 47 46 45 44 43 42 41 40 39 38 37 SADR_TRI 1 Q6 36 Q5- IN+ PLL IN- BW_SEL_TRI 2 35 Q5+ Q5 NC 3 34 OE4# NC 4 33 Q4- Q4 VDD_R 5 32 Q4+ SCLK IN+ 6 Q3 31 VDDO
GND
SDATA IN- 7 30 VDDA SADR_TRI CTRL BW_SEL_TRI LOGIC GND_R 8 Q2 29 GNDA PD# GND_DIG 9 28 OE3# Q1 SCLK 10 27 Q3- SDATA 11 26 Q3+ Q0 VDD_DIG 12 25 OE2# 13 14 15 16 17 18 19 20 21 22 23 24 O O Q0+ Q0- Q1+ Q1- V DD OE0# VDD OE1# Q2+ V DD GND Q2-
Pin Description Pin Number Pin Name Type Description
1 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down. 2 BW_SEL_TRI Input Tri-level Latch to select low-loop bandwidth, bypass PLL, and high-loop band- width. This pin has both internal pull-up and pull-down. 3 NC — — Internal connected for feedback loop. Do not connect this pin. 4 NC — — Internal connected for feedback loop. Do not connect this pin. 5 VDD_R Power — Power supply for input differential buffers 6 IN+ Input — Differential true clock input 7 IN- Input — Differential complementary clock input 8 GND_R Power — Ground for input differential buffers 9 GND_DIG Power — Ground for digital circuitry 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 11 SDATA Input/ Output CMOS SMBUS data line, 3.3V tolerant 12 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 13, 21, 31, 39, 47 VDDO Power — Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 14 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 15 Q0+ Output HCSL Differential true clock output PI6CB33801 www.diodes.com January 2020 Document Number DS41288 Rev 5-2 2 Diodes Incorporated