Datasheet 8V97003 (IDT) - 9

8V97003 Datasheet
Table 1. Pin Descriptions (Cont.) Pull-up/ Pin Number Name Type Pull-Down Description
11 CPBIAS Analog Bias node for charge pump. Connect 22µF capacitor from this pin to GND. 12 VDDPDCP Power VDD power supply for phase detector and charge pump. 13 NC Unused Do not connect. 14 VSSPDCP Ground VSS power supply ground for phase detector and charge pump. 15 VDDFB Power VDD power supply for feedback divider. 16 NC Unused Do not connect. 17 VSSFB Ground VSS power supply ground for feedback divider. 18 VDDDIG Power VDD power supply for Digital, SPI and SDM. 19 VSSDIG Ground VSS power supply ground for Digital, SPI and SDM. 20 VSSIN Ground VSS power supply ground for reference input path. 21 NC Unused Do not connect. 22 REF_IN Input PD Differential reference clock input+ (LVDS, LVPECL, CMOS). 23 nREF_IN Input PD/PU Differential reference clock input– (LVDS, LVPECL). 24 VDDIN Power VDD power supply for reference input path. 25 CSB Input PD SPI Chip Select Bar. 1.8V LVCMOS logic levels (3.3V tolerant). 26 SCLK Input SPI Clock Input. 1.8V LVCMOS logic levels (3.3V tolerant). 27 SDO Output SPI Data Output. 28 SDIO Input/Output PU SPI Data Input/ Output. 1.8V LVCMOS logic levels (3.3V tolerant). 29 CE Input PU Chip Enable. 1.8V LVCMOS logic levels (3.3V tolerant). SYNC pin can be used to implement a deterministic delay between the reference input rising edge and the output signal rising edge. 30 SYNC Input PD If not used, this pin can either be tied to ground, or left floating since it has an internal pulldown. 3.3V LVCMOS input. 31 nRESET Input PD Chip Reset. 1.8V LVCMOS logic levels (3.3V tolerant). 32 VREGVCO1 Analog Regulator for VCO. Connect 22µF capacitor from this pin to GND. 33 VDDVCO1 Power VDD power supply for VCO. 34 NC Unused Do not connect. Reference node for VCO regulator. Connect 22µF capacitor from this 35 VREFVCO1 Analog pin to GND. 36 NC Unused Do not connect. 37 VDDOUTA Power VDD output power supply for output pair A. 38 VSSOUTA Ground VSS power supply ground for output pair A. Negative side of output pair A (CML – Open Collector). The output 39 nRF_OUTA Output power level is programmable. Positive side of output pair A (CML – Open Collector). The output 40 RF_OUTA Output power level is programmable. ©2020 Renesas Electronics Corporation 9 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History