Datasheet 8V97003 (IDT) - 10

8V97003 Datasheet
Table 1. Pin Descriptions (Cont.) Pull-up/ Pin Number Name Type Pull-Down Description
41 VSSOUTA Ground VSS power supply ground for output pair A. 42 NC Analog Do not connect. 43 NC Analog Do not connect. 44 VSSOUTB Ground VSS power supply ground for output pair B. 45 RF_OUTB Output Positive side of output pair B (CML – open collector). The output power level is programmable. Negative side of output pair B (CML – open collector). 46 nRF_OUTB Output The output power level is programmable. 47 VSSOUTB Ground VSS power supply ground for output pair B. 48 VDDOUTB Power VDD output power supply output pair B. EP EPAD Ground Must be connected to ground.
Table 2. Pin Characteristics Symbol Parameter Test Condition Minimum Typical Maximum Units
CIN Input Capacitance REF_IN, nREF_IN 1 pF ROUT LVCMOS Output Impedance LD 15 Ω RPULLUP Input Pullup Resistor 50 kΩ RPULLDOWN Input Pulldown Resistor 50 kΩ
Table 3. Supply Pins and Associated Current Return Paths Power Supply Associated Ground Pin Number Pin Name Pin Number Pin Name
3 VDDVCO2 EP EPAD 12 VDDPDCP 14 VSSPDCP 15 VDDFB 17 VSSFB 18 VDDDIG 19 VSSDIG 24 VDDIN 20 VSSIN 33 VDDVCO1 EP EPAD 37 VDDOUTA 38; 41 VSSOUTA 48 VDDOUTB 44; 47 VSSOUTB ©2020 Renesas Electronics Corporation 10 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History