Datasheet ADA4254 (Analog Devices)

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier Data Sheet ADA4254 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM Optimized for ADC synchronization VDDH Low power: 22 mW (±12 V supplies) EXCITATION 12 binary gain steps from 1/16 V/V to 128 V/V CURRENTS ADA4254 IOUT_HV 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V IOUT_LV AVDD ±60 V protected input multiplexer Excellent dc precision + ROUT Low input offset voltage: ±14 µV maximum GE – UX +IN1 – –OUT Low input offset voltage drift: ±0.08 µV/°C maximum R + OLTA D M –IN1 Gain calibration via ROM V E R VOCM E CT RIN +IN2 I FILTE Low gain drift: ±1 ppm/°C maximum E T OV M + V E High CMRR: 116 dB minimum, G = 1 V/V –IN2 0 RO – +OUT 6 P ± – Low input bias current: ±1.5 nA maximum + High input impedance ROUT Integrated input EMI filtering AVSS Wide input supply range: ±5 V to ±28 V DIGITAL CONTROL DVDD Dedicated output amplifier supplies 7 × GPIO SPI INTERFACE DVSS 7 GPIO ports with special functions
001
Sequential chip select mode VSSH External multiplexer control
15741-
Excitation current sources
Figure 1.
SPI port with checksum (CRC) support Internal fault detection Wire break test currents
The input multiplexer provides ±60 V protection to the high
On-chip test multiplexer
impedance inputs of the amplifier, while providing the
28-lead, 5 mm × 5 mm LFCSP, 24-lead TSSOP
capability to switch between two input sources. In addition,
Specified temperature range: −40°C to +105°C
integrated electromagnetic interference (EMI) filters block
APPLICATIONS
harsh RF noise from the sensitive inputs of the amplifier.
Universal process control front ends
Various safety features on the ADA4254 detect both internal
Data acquisition systems
and external faults. The serial port interface (SPI) supports
Test and measurement systems
cyclical redundancy check (CRC) error detection to ensure
GENERAL DESCRIPTION
robust communication. These safety features ease system safety The ADA4254 is a zero drift, high voltage, low power integrity level (SIL) certification. programmable gain instrumentation amplifier (PGIA) designed Seven general-purpose input/output (GPIO) pins, which can be for process control and industrial applications. The ADA4254 configured to provide various special functions, are included in features 12 binary weighted gains ranging from 1/16 V/V to the ADA4254. An excitation current source output is available 128 V/V and three scaling gain options of 1 V/V, 1.25 V/V, and to bias sensors such as resistance temperature detectors (RTDs). 1.375 V/V, resulting in 36 possible gain settings. The power consumption of the ADA4254 is a mere 22 mW, making the The ADA4254 is specified over the −40°C to +105°C temperature device an excellent choice for industrial systems that demand range and is offered in a compact 5 mm × 5 mm, 28-lead LFCSP precision, robustness, and low power. and a 24-lead TSSOP. The zero drift amplifier topology of the ADA4254 self calibrates
COMPANION PRODUCTS
dc errors and low frequency 1/f noise, achieving excellent dc
ADCs: AD4007, AD7768, AD7175-2
precision over the entire specified temperature range. This high
ADC Drivers: ADA4945-1, LTC6363
level of precision maximizes dynamic range and greatly reduces
Voltage References: ADR4550, ADR3450, LT6656
calibration requirements in many applications.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER INPUT MULTIPLEXER EMI REDUCTION AND INTERNAL EMI FILTER INPUT AMPLIFIER OUTPUT AMPLIFIER POWER SUPPLIES ESD MAP OUTPUT RIPPLE CALIBRATION CONFIGURATION GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs) EXCITATION CURRENTS EXTERNAL CLOCK SYNCHRONIZATION SEQUENTIAL CHIP SELECT (SCS) GAIN ERROR CALIBRATION WIRE BREAK DETECTION TEST MULTIPLEXER EXTERNAL MUX CONTROL DIGITAL INTERFACE SPI INTERFACE ACCESSING THE ADA4254 REGISTER MAP CHECKSUM PROTECTION CRC CALCULATION MEMORY MAP CHECKSUM PROTECTION READ-ONLY MEMORY (ROM) CHECKSUM PROTECTION SPI READ/WRITE ERROR DETECTION SPI COMMAND LENGTH ERROR DETECTION APPLICATIONS INFORMATION INPUT AND OUTPUT OFFSET VOLTAGE AND NOISE ADC CLOCK SYNCHRONIZATION PROGRAMMABLE LOGIC CONTROLLER (PLC)VOLTAGE/CURRENT INPUT 3-WIRE RTD WITH CURRENT EXCITATION HIGH RAIL CURRENT SENSING REGISTER SUMMARY REGISTER DETAILS GAIN_MUX REGISTER DETAILS Bit 7, G4—Output Amplifier Scaling Gain (1.375 V/V) Bits[6:3], G[3:0]—Input Amplifier Gain Setting Bits[1:0], EXT_MUX[1:0]—External Multiplexer Control SOFTWARE RESET REGISTER (RESET) DETAILS Bit 0, RST—Soft Reset CLOCK SYNCHRONIZATION CONFIGURATION REGISTER (SYNC_CFG) DETAILS Bit 6, CLK_OUT_SEL—Clock Output Select Bit 4, SYNC_POL—Clock Synchronization Polarity Bits[2:0], SYNC[2:0]—Internal Clock Divider Value DIGITAL ERROR REGISTER (DIGITAL_ERR) DETAILS Bit 6, CAL_BUSY—Calibration Busy (Read Only) Bit 5, SPI_CRC_ERR—SPI CRC Error Bit 4, SPI_RW_ERR—SPI Read/Write Error Bit 3, SPI_SCLK_CNT_ERR—SPI SCLK Count Error Bit 1, MM_CRC_ERR—Memory Map CRC Error Bit 0, ROM_CRC_ERR—ROM CRC Error ANALOG ERROR REGISTER (ANALOG_ERR) DETAILS Bit 7, G_RST—Gain Reset Flag Bit 6, POR_HV—Power-On Reset HV Supply Bit 4, WB_ERR—Wire Break Detect Error Bit 3, FAULT_INT—Fault Interrupt Bit 2, OUTPUT_ERR—Output Amplifier Error Bit 1, INPUT_ERR—Input Amplifier Error Bit 0, MUX_OVER_VOLT_ERR—Input Multiplexer Overvoltage Error GPIO DATA REGISTER (GPIO_DATA) DETAILS Bits[6:0], GPIO_DATA[6:0]—GPIO Data Values INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input Switches Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input Switches Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test Multiplexer Switches Bit 0, SW_D12—PGIA Input Short Switch WIRE BREAK DETECT REGISTER (WB_DETECT) DETAILS Bit 7, WB_G_RST_DIS—Wire Break Gain Reset Disable Bit 3, SW_F1, and Bit 2, SW_F2—Fault Switch Selection Bits[1:0], WB_CURRENT—Detection Current Selection GPIO DIRECTION REGISTER (GPIO_DIR) DETAILS Bits[6:0], GPIO_DIR—GPIO Direction Configuration SEQUENTIAL CHIP SELECT REGISTER (SCS) DETAILS Bits[6:0], SCS—Sequential Chip Select Configuration ANALOG ERROR MASK REGISTER (ANALOG_ERR_DIS) DETAILS Bit 7, G_RST_DIS—Disable Gain Reset Error Flag Bit 6, POR_HV_DIS—Disable High Voltage Power Reset Flag Bit 4, WB_ERR_DIS—Disable Wire-Break Detection Flag Bit 3, MUX_PROT_DIS—Disable Input Multiplexer Protection Bit 2, OUTPUT_ERR_DIS—Disable Output Amplifier Error Flag Bit 1, INPUT_ERR_DIS—Disable Input Amplifier Error Flag Bit 0, MUX_OVER_VOLT_ERR_DIS—Disable Multiplexer Overvoltage Flag. DIGITAL ERROR MASK REGISTER (DIGITAL_ERR_DIS) DETAILS Bit 6, CAL_BUSY_DIS—Disable Calibration Busy Error Flag Bit 5, SPI_CRC_ERR_DIS—Disable SPI CRC Error Flag Bit 4, SPI_RW_ERR_DIS—Disable SPI Read/Write Error Flag Bit 3, SPI_SCLK_CNT_ERR_DIS—Disable SPI SCLK Count Error Flag Bit 2, M_CLK_CNT_ERR_DIS—Disable Master Clock Count Output Bit 1, MM_CRC_ERR_DIS—Disable Memory Map CRC Error Flag Bit 0, ROM_CRC_ERR_DIS—Disable ROM CRC Error Flag SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS Bit 5, INT_CLK_OUT—Internal Oscillator Output Bit 4, EXT_CLK_IN—External Oscillator Input Bit 3, FAULT_INT_OUT—Fault Interrupt Output Bit 2, CAL_BUSY_OUT—Calibration Busy Output Bits[1:0], EXT_MUX_EN[1:0]—Enable External Multiplexer Control ERROR CONFIGURATION REGISTER Bit 7, ERR_LATCH_DIS—Disable Error Latching Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS Bit 7, G5—Output Amplifier Scaling Gain = 1.25 V/V Bit 6, CAL_SEL—Calibration Type Configuration Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable and Interval Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer Configuration EXCITATION CURRENT CONFIGURATION REGISTER (EX_CURRENT_CFG) DETAILS Bits[7:6], EX_CURRENT_SEL[1:0]—Excitation Current Connection Configuration Bits[3:0], EX_CURRENT[3:0]—Excitation Current Value GAIN CALIBRATION REGISTERS (GAIN_CALx) DETAILS TRIGGER CALIBRATION REGISTER (TRIG_CAL) DETAILS Bit 0, TRIG_CAL—Trigger Calibration Input MASTER CLOCK COUNT REGISTER (M_CLK_CNT) DETAILS Bits[7:0], M_CLK_CNT[7:0]—Master Clock Count DIE REVISION IDENTIFICATION REGISTER (DIE_REV_ID) DETAILS Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number DEVICE IDENTIFICATION REGISTERS (PART_ID) DETAILS PART_ID[39:0]—Part ID Number OUTLINE DIMENSIONS ORDERING GUIDE