Datasheet TLP5231 (Toshiba) - 10

TLP5231 11.2. Switching Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 , VCC2 - VE = 15 V, VE - VEE = 8 V) Test Characteristics Symbol Note Test Condition Min Typ. Max Unit Circuit Propagation delay time t1 (Note 1) Fig.13.1.18 CP = CN = 4 nF, CG = 1 nF,  450 750 ns from DESAT threshold to f = 100 Hz, duty = 50 %, 50% of high VGMOS IF = 8 mA, CBLANK = 200 pF, Propagation delay time t VDESAT = 8.0 V 2  380 700 from DESAT threshold to 50% of high VOUTP Propagation delay time t3 RF = 10 kΩ, CF = 1 nF,  8 20 µs from DESAT threshold to VCC1 = 3.3 or 5 V, f = 100 Hz, 50% of high VFAULT duty = 50 %, IF = 8 mA Propagation delay time t4 CP = CN = 4 nF, CG = 1 nF,  45  ns from 50% VGMOS to 50% f = 100 Hz, duty = 50 %, of VOUTN IF = 8 mA DESAT Mute time tMUTE (Note 2) IF = 8 mA 0.68 1.1 1.7 ms DESAT leading edge tDESAT (Note 3)   580  ns blanking time (LEB) DESAT filter time tDESAT (Note 4) RDESAT = 100 Ω, Vin = 10 V,  290  (FILTER) PW = 1 µs, monitor: VOUTP, VGMOS High-level common-mode CMH (Note 5) Fig.13.1.19, Ta = 25 , |VCM| = 1500 Vp-p, ±25   kV/µs transient immunity Fig.13.1.21 VCC1 = 5 V (IF = 0 mA), Rin = 220 Ω (with split resistors) Low-level common-mode CML (Note 6) Fig.13.1.20, Ta = 25 , |VCM| = 1500 Vp-p, ±25   transient immunity Fig.13.1.22 VCC1 = 5 V (IF = 8 mA), Rin = 220 Ω (with split resistors) Note: All typical values are at Ta = 25 . CG means the external MOSFET gate capacitance for soft gate turn-off. Note 1: Input signal duty = 50 %, tr = tf = 5 ns or less Note 2: Automatic reset time from protected operation.If the input voltage of a DESAT pin exceeds VDESAT, VOUTP moves to high level, VOUTN set to low level, VGMOS moves to high level and FAULT moves to high level, then protected operation will start. If a gate input signal returns to a low level, automatic reset of the protected operation will be carried out after tMUTE. Refer to Fig. 13.2.2 and Fig. 13.2.3. Note 3: Disabling time for incorrect detection prevention in case a gate control signal inputs.Refer to Fig. 13.2.2. Note 4: Disabling time for incorrect detection prevention when the input voltage to a DESAT pin exceeds VDESAT. ( tDESAT(FILTER) < t1, t2 ) Note 5: CMH is the maximum rate of fall of the common mode voltage that can sustained with the output voltage in the logic high state (VOUTP - VE > 12 V, VOUTN - VEE > 5 V or VFAULT > 2 V). Note 6: CML is the maximum rate of rise of the common mode voltage that can sustained with the output voltage in the logic low state (VOUTP - VE < 1 V, VOUTN - VEE < 1 V or VFAULT < 0.8 V). ©2019-2020 10 2020-03-02 Toshiba Electronic Devices & Storage Corporation Rev.2.0