Datasheet VIPER222 (STMicroelectronics) - 9

VIPER222 General description 6 General description
VIPER222 is a 730 V high voltage converter optimized for flyback and buck topologies that operates at 60 kHz (L type) or 30 kHz (X type) switching frequency and integrates the jittering feature in order to reduce the EMI level. The low IC consumption combined with the burst mode technique allow to obtain very low input power at no load and very good efficiency at light load.
6.1 Startup
At the first startup the integrated high voltage current source charges the VCC capacitor. At the beginning of startup, when the capacitor is fully discharged, the charging current is low, ICH1, in order to avoid IC damaging in case VCC is accidentally shorted to GND. As VCC exceeds 1 V, ICH1 is increased to ICH2 in order to speed up the charging. The charge current is stopped as soon as VCC reaches VON. As soon as the VCC capacitor is charged up to VON, the high voltage current source is disabled, the device is powered by the energy stored in the capacitor and the primary MOSFET starts switching. The internal soft-start function of the device progressively increases the cycle-by-cycle current limitation set point from zero up to ILIM in 8 steps. The soft-start time, tSS, is internally set at 8 ms. This function is activated at any attempt of converter startup and at any restart after a fault event.
6.2 Feedback loop
The device operates in current mode, so the primary current is internally sensed and converted in voltage that is applied to the non-inverting pin of the PWM comparator. The sensed voltage is compared through a voltage divider and on cycle-by-cycle basis with the one present on the EA-IN pin. The OCP comparator works in parallel with the PWM comparator and it limits the primary current below the ILIM threshold. There are two ways to close the loop and get the output regulated: through resistor divider or through external error amplifier plus optocoupler
Resistor divider
For non-isolated topologies (fly-back, buck or buck-boost converters) the output voltage can be directly set connecting a resistor divider (referenced to GND pin) between the converter output and the EA-IN pin, which is the inverting input of the integrated error amplifier (EA). Primary side regulation can be realized connecting the resistor divider between VCC, EA-IN and GND pins. The loop compensation network is connected across EA-OUT and GND pins.
External error amplifier plus optocoupler
In case of isolated fly-back, EA-IN must be connected to GND, which disables the internal error amplifier, and the output voltage is set through an external error amplifier (TL431 or similar) placed on the secondary side. Its error signal, reported to the primary through an optocoupler, is used to set the EA-OUT pin voltage to the value corresponding to the DRAIN peak current required by the control loop to deliver the given output power. The EA-OUT pin dynamics range between the values VEA-BM and VEA-SAT: below the VEA-BM level the device enters burst mode; above the VEA-SAT level, the primary drain current reaches its limit ILIM.
6.3 Pulse skipping
The protection is intended to avoid the so called “flux-runaway” condition often present at converter startup, because of the low output voltage, and due to the fact that the primary MOSFET, cannot be turned off before the minimum on-time. During the on-time, the inductor is charged by the input voltage and if it cannot be discharged by the same amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that can reach dangerously high values.
DS13192
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Rev 2 page 9/20
Document Outline Cover image Product status link / summary Features Application Description 1 Pin setting 2 Typical power capability 3 Electrical and thermal ratings 4 Electrical characteristics 5 Typical electrical characteristics 6 General description 6.1 Startup 6.2 Feedback loop 6.3 Pulse skipping 6.4 Burst mode at light load 6.5 Short-circuit protection 6.6 VCC clamp protection 7 Basic application schematics 8 Package information 8.1 SSOP10 package information Revision history Contents List of tables List of figures