Datasheet TPD7107F (Toshiba) - 9

TPD7107F 7.6. Over current protection
● When the current sense voltage (VDIAG) turns into more than over-current detecting voltage (VOC), the rapid of -driver operates to protect the external FET. After that, it becomes an OFF & latch state and outputs diagnostic contents. ● The filter (Over current detection delay time 2.5us (typ.)) is built in so that the over-current caused by a power supply variation may not be detected incorrectly. ● In case VIN=H to L, the over current protection circuit releases latches. When a latch of DIAG is released, the clear standby time from the fal ing edge of VIN(TDIAG) is set to 10ms (minimum). In a period of the standby time, the IN terminal cannot control the GATE terminal. Normal. OC. Normal. TDIAG VIN Latch off. VGATE VDIAG VOC VDIAG T OC TLATCH ● VIN: IN pin input voltage ● VGATE: GATE pin output voltage ● VDIAG: DIAG pin output voltage ● VOC: Over current detection voltage ● VDIAG1: DIAG output voltage (High Level) ● TOC: Over current detection delay time ● TLATCH: Latch release mask time ● TDIAG: DIAG clear standby time
Figure 7.9 Over current protection
● The over current threshold voltage changes according to the power supply voltage and the junction temperature. ‒ VOC1: VDD=3V,Tj=25°C ‒ VOC2: Tj=25°C ‒ VOC3: VDD=3V,Tj=125°C ‒ VOC4: Tj=125°C ● The over current detecting voltage fal s to 66% (typ.) of VOC2 and VOC4, when the abnormalities in voltage between drain and source of the external FET occur. ● The over current detection voltage fal s to 50% (typ.) of VOC2 and VOC4, when the under voltage detection (UV5) occurs. © 2 020 9 2020-04-09 Toshiba Electronic Devices & Storage Corporation Document Outline 1. Description 2. Uses 3. Features 4. Block Diagram 5. Pin Assignments 6. Pin Description 7. Operational Description 7.1. Protection for reverse connection of power supply 7.2. Active clamp 7.3. Gate drive of Power MOSFET (Off driver) 7.3.1. Normal off, rapid off 7.3.2. Protection for disconnection of GND terminal 7.4. Load current sense at time of Power MOSFET drive 7.5. The abnormalities in power supply voltage (VDD over voltage, VDD under voltage) 7.6. Over current protection 7.7. Over temperature protection. 7.8. Abnormalities in voltage between Drain and source of the external FET (VDS error) 7.9. Load open / VDD short of load line and diagnosis output 7.10. Truth Table 7.11. State Transition Diagram 8. Absolute Maximum Ratings 8.1. Thermal Resistance 9. Operating Ranges 10. Electrical Characteristics 10.1. Electrical characteristics 1 10.2. Electrical characteristics 2 10.3. Current sense amp Electrical Characteristics 11. Test Circuit 11.1. Test circuit 1 High level output voltage (3) 11.2. Test circuit 2 Switching time (Td-ON, Td-OFF, Tr, Tf) 11.3. Test circuit 3 Off impedance at GND open 11.4. Test circuit 4 Input offset voltage 12. Characteristic curves 13. Package Information 13.1. Package Dimensions 13.2. Marking 13.3. Land Pattern Dimensions for Reference only 14. IC Usage Notes 14.1. Notes on Handling of ICs 14.2. Notes on mounting. RESTRICTIONS ON PRODUCT USE