Datasheet AD8005 (Analog Devices) - 10

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AD8005 Data Sheet APPLICATIONS DRIVING CAPACITIVE LOADS R2 1.5kΩ
Capacitive loads interact with the output impedance of an op
5V
amp to create an extra delay in the feedback path. This reduces circuit stability and can cause unwanted ringing and oscillation.
R1 1.5kΩ 0.01µF 10µF
A given value of capacitance causes much less ringing when the
VIN AD8005
amplifier is used with a higher noise gain.
VOUT VREF
The capacitive load drive of the AD8005 can be increased by
5V R3 R4
adding a low valued resistor in series with the capacitive load.
30.1kΩ 10kΩ
Introducing a series resistor tends to isolate the capacitive load
0.1µF
032 from the feedback loop, thereby diminishing its influence. 12146- Figure 31 shows the effects of a series resistor on capacitive drive Figure 32. Bipolar to Unipolar Shift Lever for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with Figure 32 shows a level shifter circuit that can move a bipolar less overshoot. Adding a series resistor at lower closed-loop signal into a unipolar range. A positive reference voltage, derived gains accomplishes the same effect. For large capacitive loads, from the +5 V supply, sets a bias level of +1.25 V at the nonin- the frequency response of the amplifier is dominated by the verting terminal of the op amp. In ac applications, the accuracy roll-off of the series resistor and capacitive load. of this voltage level is not important; however, noise is a serious
R
consideration. A 0.1 mF capacitor provides useful decoupling of
F
this noise. The bias level on the noninverting terminal sets the input common-
R R S G AD8005
mode voltage to +1.25 V. Because the output is always positive,
RL
the op amp can be powered with a single +5 V power supply.
1kΩ CL
030 The overall gain function is given by the equation: 12146- Figure 30. Driving Capacitive Loads  R2   R4   R2  =  −  +   1+ OU V T VIN   R V EF 
80
R1   R3 + R4   R1 
VS = ±5V 2V OUTPUT STEP
In the above example, the equation simplifies to
70 WITH 30% OVERSHOOT
VOUT = −VIN + 2.5 V
60 pF) ( RS = 10Ω SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION D 50
Many single supply ADCs have differential inputs. In such
LOA R E 40 S = 5Ω
cases, the ideal common-mode operating point is usually
ITIV C 30
halfway between supply and ground. Figure 33 shows how to
A P A R
convert a single-ended bipolar signal into a differential signal
C S = 0Ω 20
with a common-mode level of 2.5 V.
10 +5V +5V 2.49kΩ 0 0.1µF RIN 0.1µF 1 2 3 4 5
031
BIPOLAR 1kΩ SIGNAL CLOSED-LOOP GAIN (V/V)
12146-
±0.5V AD8005
Figure 31. Capacitive Load Drive vs. Closed-Loop Gain
2.49kΩ R SINGLE-SUPPLY LEVEL SHIFTER F1 2.49kΩ
In addition to providing buffering, many systems require that an
RG RF1 619Ω V 3.09kΩ OUT
op amp provide level shifting. A common example is the level
+5V
shifting required to move a bipolar signal into the unipolar range
0.1µF
of many modern analog-to-digital converters (ADCs). In general,
+5V
single supply ADCs have input ranges that are referenced neither
AD8005 2.49kΩ
to ground nor supply. Instead the reference level is some point in between, usually halfway between ground and supply (+2.5 V
2.49kΩ 0.1µF
033 for a single supply 5 V ADC). Because high-speed ADCs typically 12146- have input voltage ranges of 1 V to 2 V, the op amp driving it Figure 33. Single-Ended-to-Differential Converter must be single supply but not necessarily rail-to-rail. Rev. B | Page 10 of 16 Document Outline Features Applications General Description Functional Block Diagrams Table of Contents Revision History Specifications ±5 V Supplies +5 V Supply Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Typical Performance Characteristics Applications Driving Capicative Loads Single-Supply Level Shifter Single-Ended-to-Differential Conversion Layout Considerations Increasing Feedback Resistors Outline Dimensions Ordering Guide