Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 4
| 制造商 | Microchip |
| 描述 | Two-Port Ethernet Switch with Non-PCI Interface |
| 页数 / 页 | 132 / 4 — KSZ8842-16M/-32M. 1.0. INTRODUCTION. 1.1. General Description. FIGURE … |
| 文件格式/大小 | PDF / 3.0 Mb |
| 文件语言 | 英语 |
KSZ8842-16M/-32M. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. SYSTEM BLOCK DIAGRAM
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KSZ8842-16M/-32M 1.0 INTRODUCTION 1.1 General Description
The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces, and are available in 8-/16-bit and 32- bit bus designs. This data sheet describes the KSZ8842M-series of non-PCI CPU interface chips. For information on the KSZ8842 PCI CPU interface switches, refer to the KSZ8842P data sheet. The KSZ8842M is the industry’s first fully managed, 2-port switch with a non-PCI CPU interface. It is based on a proven, 4th generation, integrated Layer-2 switch, compliant with IEEE 802.3u standards. Also an industrial temperature grade version of the KSZ8842, the KSZ8842MVLI, can be ordered. The KSZ8842M can be configured as a switch or as a low-latency (≤310 nanoseconds) repeater in latency-critical, embedded or industrial Ethernet applications. For industrial applications, the KSZ8842M can run in half-duplex mode regardless of the application. The KSZ8842M offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority man- agement, management information base (MIB) counters, and CPU control/data interfaces to effectively address Fast Ethernet applications. The KSZ8842M contains two 10/100 transceivers with patented, mixed-signal, low-power technology, two media access control (MAC) units, a direct memory access (DMA) channel, a high-speed, non-blocking, switch fabric, a dedicated 1K entry forwarding table, and an on-chip frame buffer memory.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
1K Look-Up Engine HP Auto 10/100 10/100 MDI/MDI-X T/TX MAC 1 PHY 1 FIFO, Flow Control, Queue HP Auto 10/100 Management 10/100 MDI/MDI-X T/TX MAC 2 PHY 2 VLAN Tagging ,Priority Buffer 10/100 Management MAC 3 Embedded Non-PCI Processor Interface CPU Bus Interface Unit Frame Buffers 8/16/32 Bit Generic Host Interface MIB Counters Control EEPROM Registers Interface EEPROM I/F P1 LED[2:0] Strap In LED Drivers Configuration Pins P2 LED[2:0] DS00003459A-page 4 2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces, and are available in 8-/16-bit and 32- bit bus designs. This data sheet describes the KSZ8842M-series of non-PCI CPU interface chips. For information on the KSZ8842 PCI CPU interface switches, refer to the KSZ8842P data sheet. The KSZ8842M is the industry’s first fully managed, 2-port switch with a non-PCI CPU interface. It is based on a proven, 4th generation, integrated Layer-2 switch, compliant with IEEE 802.3u standards. Also an industrial temperature grade version of the KSZ8842, the KSZ8842MVLI, can be ordered. The KSZ8842M can be configured as a switch or as a low-latency (≤310 nanoseconds) repeater in latency-critical, embedded or industrial Ethernet applications. For industrial applications, the KSZ8842M can run in half-duplex mode regardless of the application. The KSZ8842M offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority man- agement, management information base (MIB) counters, and CPU control/data interfaces to effectively address Fast Ethernet applications. The KSZ8842M contains two 10/100 transceivers with patented, mixed-signal, low-power technology, two media access control (MAC) units, a direct memory access (DMA) channel, a high-speed, non-blocking, switch fabric, a dedicated 1K entry forwarding table, and an on-chip frame buffer memory.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
1K Look-Up Engine HP Auto 10/100 10/100 MDI/MDI-X T/TX MAC 1 PHY 1 FIFO, Flow Control, Queue HP Auto 10/100 Management 10/100 MDI/MDI-X T/TX MAC 2 PHY 2 VLAN Tagging ,Priority Buffer 10/100 Management MAC 3 Embedded Non-PCI Processor Interface CPU Bus Interface Unit Frame Buffers 8/16/32 Bit Generic Host Interface MIB Counters Control EEPROM Registers Interface EEPROM I/F P1 LED[2:0] Strap In LED Drivers Configuration Pins P2 LED[2:0] DS00003459A-page 4 2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service