Datasheet KSZ8852HLE (Microchip) - 10

KSZ8852HLE TABLE 2-1: SIGNALS FOR KSZ8852HLE Pin Pin Name Type Description Number
1 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential). 2 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential). 3 AGND GND Analog ground. 4 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential). 5 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential). 6 VDD_AL P This pin is used as an input for the low voltage analog power. Its source should have appropriate filtering with a ferrite bead and capacitors.
Current Set
7 ISET O Sets the physical transmit output current. Pull down this pin with a 6.49 kΩ (1%) resistor to ground. 8 AGND GND Analog ground. 9 VDD_A3.3 P 3.3V analog VDD input power supply with well decoupling capacitors. 10 RXM2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (– differential). 11 RXP2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential). 12 AGND GND Analog ground. 13 TXM2 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential). 14 TXP2 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential). 15 N/U I This unused input should be connected to GND. This pin is used as a second input for the low voltage analog power. Its 16 VDD-COL P source should have appropriate filtering with a ferrite bead and capacitors.
Full Chip Power-Down
Active-Low (Low = power down; High or floating = normal operation). While this pin is asserted low, all I/O pins will be tri-stated. All registers will 17 PWRDN IPU be set to their default state. While this pin is asserted, power consumption will be minimal. When the pin is de-asserted power consumption will climb to nominal and the device will be in the same state as having been reset by the reset pin (RSTN, pin 63). 18 X1 I
25 MHz Crystal or Oscillator Clock Connection
Pins (X1, X2) connect to a crystal or frequency oscillator source. If an oscil- lator is used, X1 connects to a VDD_IO voltage tolerant oscillator and X2 is 19 X2 O a no connect. This clock requirement is ±50 ppm. 20 DGND GND Digital ground. 3.3V, 2.5V, or 1.8V digital V 21 VDD_IO P DD input power pin for IO logic and the internal Low Voltage regulator.
Shared Data Bus Bit[15] or BE3
This is data bit (D15) access when CMD = “0”. This is Byte Enable 3 (BE3, I/O 22 SD15/BE3 4th byte enable and active-high) at double-word boundary access in 16-bit (PD) bus mode when CMD = “1”. This pin must be tied to GND in 8-bit bus mode. DS00002761A-page 10  2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service