Datasheet KSZ8873MML (Microchip) - 5
| 制造商 | Microchip |
| 描述 | Integrated 3-Port 10/100 Managed Switch with PHY |
| 页数 / 页 | 91 / 5 — KSZ8873MML. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 64-PIN … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
KSZ8873MML. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 64-PIN 10 MM X 10 MM LQFP ASSIGNMENT, (TOP VIEW)
该数据表的模型线
文件文字版本
KSZ8873MML 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 64-PIN 10 MM X 10 MM LQFP ASSIGNMENT, (TOP VIEW)
1 P2LED0 P2LED1 P1LED0 P1LED1 SMTXEN1 VDDCO GND VDDIO SMTXC1 SMTXD10 SMTXD1 SMTXD12 SMTXD13 SMTXER1/MII_LINK_1 SMRXDV1 SMRXD10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSTN 1 48 SMRXD11 VDDA_1.8 2 47 SMRXD12 AGND 3 46 SMRXD13 NC 4 45 SMRXC1 NC 5 44 SCOL1 VDDA_3.3 6 43 SCRS1 AGND 7 42 SDA_MDIO ISET 8 41 SCL_MDC VDDA_1.8 9 40 INTRN RXM2 10 39 SPISN RXP2 11 38 SPIQ AGND 12 37 VDDC TXM2 13 36 GND TXP2 14 35 SMRXC3 NC 15 34 SCOL3 PWRDN 16 33 SCRS3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 GND VDDIO SMTXC3 SMTXEN3 SMTXD33 SMTXD32 SMTXD31 SMTXD30 SMRXDV3 SMRXD33 SMRXD32 SMRXD31 SMRXD30 SMTXER3/MII_LINK_3 2018 Microchip Technology Inc. DS00002776A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
1 P2LED0 P2LED1 P1LED0 P1LED1 SMTXEN1 VDDCO GND VDDIO SMTXC1 SMTXD10 SMTXD1 SMTXD12 SMTXD13 SMTXER1/MII_LINK_1 SMRXDV1 SMRXD10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSTN 1 48 SMRXD11 VDDA_1.8 2 47 SMRXD12 AGND 3 46 SMRXD13 NC 4 45 SMRXC1 NC 5 44 SCOL1 VDDA_3.3 6 43 SCRS1 AGND 7 42 SDA_MDIO ISET 8 41 SCL_MDC VDDA_1.8 9 40 INTRN RXM2 10 39 SPISN RXP2 11 38 SPIQ AGND 12 37 VDDC TXM2 13 36 GND TXP2 14 35 SMRXC3 NC 15 34 SCOL3 PWRDN 16 33 SCRS3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 GND VDDIO SMTXC3 SMTXEN3 SMTXD33 SMTXD32 SMTXD31 SMTXD30 SMRXDV3 SMRXD33 SMRXD32 SMRXD31 SMRXD30 SMTXER3/MII_LINK_3 2018 Microchip Technology Inc. DS00002776A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service