Datasheet KSZ8873MML (Microchip) - 7

KSZ8873MML TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
Switch port 3 MII transmit error in MII mode SMTXER3/ 27 IPU 0 = MII link indicator from host in MII PHY mode. MII_LINK_3 1 = No link on port 3 MII PHY mode and enable Bypass mode. Switch MII receive data valid Strap option: MII mode selection for port 3 28 SMRXDV3 IPU/O PU = PHY mode. PD = MAC mode (In MAC mode, port 3 MII has to connect to a powered active external PHY for the normal operation) Switch MII receive data bit 3 Strap option: enable auto-negotiation on port 2 (P2ANEN) 29 SMRXD33 IPU/O PU = Enable PD = Disable Switch MII receive data bit 2 Strap option: Force the speed on port 2 (P2SPD) 30 SMRXD32 IPU/O PU = Force port 2 to 100BT if P2ANEN = 0 PD = Force port 2 to 10BT if P2ANEN = 0 Switch MII receive data bit 1 Strap option: Force duplex mode (P2DPX) PU = Port 2 default to full-duplex mode if P2ANEN = 1 and auto-negotiation 31 SMRXD31 IPU/O fails. Force port 2 in full-duplex mode if P2ANEN = 0. PD = Port 2 set to half-duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half-duplex mode if P2ANEN = 0. Switch MII receive data bit 0 Strap option: Force flow control on port 2 (P2FFC) 32 SMRXD30 IPU/O PU = Always enable (force) port 2 flow control feature. PD = Port 2 flow control feature enable is determined by auto-negotiation result. 33 SCRS3 IPU/O Switch MII carrier sense 34 SCOL3 IPU/O Switch MII collision detect Switch MII receive clock. 35 SMRXC3 I/O Output in PHY MII mode Input in MAC MII mode 36 GND GND Digital ground 37 VDDC P 1.8V digital core power input from VDDCO (pin 59). SPI slave mode: serial data output 38 SPIQ IPU/O Note: an external pull-up is needed on this pin when it is in use. SPI slave mode: chip select (active low) When SPISN is high, the KSZ8873MML is deselected and SPIQ is held in 39 SPISN IPU high impedance state. A high-to-low transition is used to initiate SPI data transfer. Note: An external pull-up is needed on this pin when it is in use. Interrupt 40 INTRN OPU Active Low signal to host CPU to indicate an interrupt status bit is set. Refer to register 187 and 188.  2018 Microchip Technology Inc. DS00002776A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service