Datasheet KSZ8895MLUB (Microchip) - 88
| 制造商 | Microchip |
| 描述 | Integrated 5-Port 10/100 Managed Switch |
| 页数 / 页 | 100 / 88 — KSZ8895MLUB. FIGURE 7-7:. PHY MODE MII TIMING - DATA RECEIVED FROM MII. … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
KSZ8895MLUB. FIGURE 7-7:. PHY MODE MII TIMING - DATA RECEIVED FROM MII. FIGURE 7-8:
该数据表的模型线
- KSZ8895FQXC KSZ8895FQXC-TR KSZ8895FQXCA KSZ8895FQXI KSZ8895FQXI-TR KSZ8895FQXIA KSZ8895ML KSZ8895MLUB KSZ8895MLUB-TR KSZ8895MLXC KSZ8895MLXC-TR KSZ8895MLXI KSZ8895MLXI-TR KSZ8895MQ KSZ8895MQI KSZ8895MQXC KSZ8895MQXC-TR KSZ8895MQXCA KSZ8895MQXI KSZ8895MQXI-TR KSZ8895MQXIA KSZ8895RQI KSZ8895RQXC KSZ8895RQXC-TR KSZ8895RQXCA KSZ8895RQXCA-TR KSZ8895RQXI KSZ8895RQXI-TR KSZ8895RQXIA SPNY801156 SPNY801159 SPNY801159-TR SPNY801160 SPNY801160-TR SPNY801171 SPNY801172 SPNY801172-TR SPNZ801156 SPNZ801159 SPNZ801159-TR SPNZ801160 SPNZ801160-TR SPNZ801161 SPNZ801171 SPNZ801172
文件文字版本
KSZ8895MLUB FIGURE 7-7: PHY MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-8: PHY MODE MII TIMING - DATA TRANSMITTED FROM MII TABLE 7-4: PHY MODE MII TIMING PARAMETERS 10BASE-T/100BASE-TX Symbol Parameter Min. Typ. Max. Units
tCYC4 Clock Cycle — 400/40 — ns tS4 Setup Time 10 — — ns tH4 Hold Time 0 — — ns tOV4 Output Valid 16 20 25 ns DS00002680A-page 88 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
tCYC4 Clock Cycle — 400/40 — ns tS4 Setup Time 10 — — ns tH4 Hold Time 0 — — ns tOV4 Output Valid 16 20 25 ns DS00002680A-page 88 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service