Datasheet KSZ8993M (Microchip) - 4
| 制造商 | Microchip |
| 描述 | Integrated 3-Port 10/100 Managed Switch with PHYs |
| 页数 / 页 | 74 / 4 — KSZ8993M. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. … |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
KSZ8993M. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. SYSTEM BLOCK DIAGRAM
该数据表的模型线
文件文字版本
KSZ8993M 1.0 INTRODUCTION 1.1 General Description
The KSZ8993M, a highly integrated Layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address a wide range of Fast Ethernet applications. The KSZ8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high speed non-blocking switch fabric, a dedicated address lookup engine, and an on- chip frame buffer memory. Both PHY units support 10BASE-T and 100BASE-TX. In addition, one of the PHY unit supports 100BASE-FX. The KSZ8993ML is the single supply version with the same features of the KSZ8993M.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
1K Look-Up Engine 10/100 AUTO 10/100 T/TX/FX MAC 1 MDI/MDI-X PHY 1 FIFO Queue Management , F 10/100 lo AUTO 10/100 w C T/TX MAC 2 MDI/MDI-X PHY 2 ontr Buffer ol Management , VLAN 10/100 MII/SNI MAC 3 Tagg Frame ing Buffers , P r SNI iorit y MIB SPI SPI Counters MIIM Control EEPROM Registers Interface SMI I2C P1 LED[3:0] LED Strap-In Drivers Configuration Pins P2 LED[3:0] DS00003066A-page 4 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
The KSZ8993M, a highly integrated Layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address a wide range of Fast Ethernet applications. The KSZ8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high speed non-blocking switch fabric, a dedicated address lookup engine, and an on- chip frame buffer memory. Both PHY units support 10BASE-T and 100BASE-TX. In addition, one of the PHY unit supports 100BASE-FX. The KSZ8993ML is the single supply version with the same features of the KSZ8993M.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
1K Look-Up Engine 10/100 AUTO 10/100 T/TX/FX MAC 1 MDI/MDI-X PHY 1 FIFO Queue Management , F 10/100 lo AUTO 10/100 w C T/TX MAC 2 MDI/MDI-X PHY 2 ontr Buffer ol Management , VLAN 10/100 MII/SNI MAC 3 Tagg Frame ing Buffers , P r SNI iorit y MIB SPI SPI Counters MIIM Control EEPROM Registers Interface SMI I2C P1 LED[3:0] LED Strap-In Drivers Configuration Pins P2 LED[3:0] DS00003066A-page 4 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service