Datasheet LAN9312 (Microchip) - 3

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface General Description
The LAN9312 is a full featured, 2 port 10/100 managed Ethernet switch designed for embedded
applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9312 combines all the functions of a 10/100 switch system, including the switch fabric, packet
buffers, buffer manager, media access controllers (MACs), PHY transceivers, and host bus interface.
The LAN9312 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet
protocol specification and 802.1D/802.1Q network management protocol specifications, enabling
compatibility with industry standard Ethernet and Fast Ethernet applications.
At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The
switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and
priority tagged frames. The switch fabric provides an extensive feature set which includes spanning
tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by
VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of
prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while
forwarding operations are completed, and a 1K entry forwarding table provides ample room for MAC
address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each
queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is
managed dynamically via the buffer manager block within the switch fabric. All aspects of the switch
fabric are managed via the switch fabric configuration and status registers, which are indirectly
accessible via the memory mapped system control and status registers.
The LAN9312 provides 2 switched ports. Each port is fully compliant with the IEEE 802.3 standard and
all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The
LAN9312 provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the Host MAC
are used to connect the LAN9312 switch fabric to the host bus interface. All ports support automatic
or manual full duplex flow control or half duplex backpressure (forced collision) flow control. Automatic
32-bit CRC generation/checking and automatic payload padding are supported to further reduce CPU
overhead. 2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively
increasing throughput while deceasing CPU load. All MAC and PHY related settings are fully
configurable via their respective registers within the LAN9312.
The integrated Host Bus Interface (HBI) easily interfaces to most 32-bit embedded CPU’s via a simple
SRAM like interface, enabling switch fabric access via the internal Host MAC and allowing full control
over the LAN9312 via memory mapped system control and status registers. The HBI supports 32-bit
operation with big, little, and mixed endian operations. Four separate FIFO mechanisms (TX/RX Data
FIFO’s, TX/RX Status FIFO’s) interface the HBI to the Host MAC and facilitate the transferring of
packet data and status information between the host CPU and the switch fabric. The LAN9312 also
provides power management features which allow for wake on LAN, wake on link status change
(energy detect), and magic packet wakeup detection. A configurable host interrupt pin allows the
device to inform the host CPU of any internal interrupts.
The LAN9312 contains an I2C/Microwire master EEPROM controller for connection to an optional
EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can
be optionally configured to automatically load stored configuration settings from the EEPROM into the
LAN9312 at reset.
In addition to the primary functionality described above, the LAN9312 provides additional features
designed for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT),
a 32-bit 25MHz free running counter, a 12-bit configurable GPIO/LED interface, and IEEE 1588 time
stamping on all ports and select GPIOs. The IEEE time stamp unit provides a 64-bit tunable clock for
accurate PTP timing and a timer comparator to allow time based interrupt generation.
The LAN9312’s performance, features and small size make it an ideal solution for many applications
in the consumer electronics and industrial automation markets. Targeted applications include: set top
boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP and video phone
systems, home gateways, and test and measurement equipment. System-level and block-level
diagrams of the LAN9312 can be seen in on the following pages. SMSC LAN9312 3 PRODUCT PREVIEW Revision 2.0 (02-14-13)